METHOD FOR MANUFACTURING TRANSISTORS AND ASSOCIATED SUBSTRATE

• US 20150076620A1
• Filed: 09/11/2014
• Published: 03/19/2015
• Est. Priority Date: 09/11/2013
• Status: Abandoned Application

• Current Assignee: IMEC International
• Original Assignee: IMEC International
• Inventors: WALDRON, Niamh, WITTERS, Liesbeth
• Application Number:
  US14/484,070
• Publication Number:
  US 20150076620A1
• Time in Patent Office: Days
• US Class Current: 257/401
• CPC Class Codes: H01L 21/762 Dielectric regions , e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823821 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823878 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 21/8258 the substrate being a semiconductor, using a combination of technologies covered by H01L21/8206, H01L21/8213 , H01L21/822, H01L21/8252, H01L21/8254 or H01L21/8256
• CPC Class Codes: H01L 27/0922 Combination of complementary transistors having a different structure, e.g. stacked CMOS, high-voltage and low-voltage CMOS
• CPC Class Codes: H01L 27/0924 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/045 by their particular orientation of crystalline planes
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/161 including two or more of the elements provided for in group H01L29/16 , e.g. alloys H01L29/1604 takes precedence
• CPC Class Codes: H01L 29/20 including, apart from doping materials or other impurities, only AIIIBV compounds
• CPC Class Codes: H01L 29/267 in different semiconductor regions , e.g. heterojunctions H01L29/263 takes precedence

Abstract

The disclosed technology generally relates to semiconductor devices, and more particularly to different types of transistors having different channel materials. In one aspect, a method of fabricating a semiconductor device includes providing a substrate comprising a silicon substrate having a main surface oriented in a {100} crystal plane and having a notch oriented in a <100> direction. The method additionally includes forming a plurality of silicon protrusions in a first predetermined region by recessing portions of the main surface surrounding the silicon protrusions. The method additionally includes forming shallow trench isolation (STI) structures adjacent to the silicon protrusions to electrically isolate the silicon protrusions, thereby defining channel areas of a transistor of a first type. The method further includes removing at least upper portions of the silicon protrusions, thereby forming trenches between neighboring STI structures and filling the trenches with a III-V material.

Claims

1. A method of fabricating a semiconductor device, comprising

providing a substrate comprising a silicon substrate having a main surface oriented in a {100} crystal plane and having a notch oriented in a <

100>

direction;

forming a plurality of silicon protrusions in a first predetermined region by recessing portions of the main surface surrounding the silicon protrusions;

forming shallow trench isolation (STI) structures adjacent to the silicon protrusions to electrically isolate the silicon protrusions, thereby defining channel areas of a transistor of a first type;

removing at least upper portions of the silicon protrusions, thereby forming trenches between neighboring STI structures; and

filling the trenches with a III-V material.

2. The method of claim 1,

wherein providing the substrate further comprises:

forming a dielectric bonding layer on top of the main surface,

bonding a semiconductor layer on the silicon substrate using the dielectric bonding layer, wherein the semiconductor layer has a lattice constant that is different from a lattice constant of the silicon substrate, and

removing a portion of the semiconductor layer and the dielectric bonding layer to expose the underlying silicon substrate in the first predetermined region for forming the transistor device of the first type, while leaving a remaining portion of the semiconductor layer in a second predetermined region for forming a transistor device of a second type; and

wherein filling the trenches includes epitaxially growing a III-V material in the trenches, thereby forming channel structures of the transistors of the first type that are substantially defect-free; and

wherein the method further comprises patterning the semiconductor layer in the second predetermined region to form channel structures of the transistors of the second type.

3. The method of claim 2, wherein the semiconductor layer comprises a material selected from the group consisting of germanium (Ge), silicon-germanium (Si_xGe_1-x), germanium-tin (Ge_xSn_1-x) and/or III-V materials a and a combination thereof.

4. The method of claim 3, wherein the semiconductor layer consists essentially of germanium.

5. The method of claim 3, wherein a stress level of the semiconductor layer is between −

5 GPa and +5 GPa.

6. The method of claim 2, wherein the channel structures of the transistors of the first type comprise a III-V material layer or stack comprising a material chosen from the group consisting of InP, In_xAl_1-xAs, In_xGa_1-xAs, In_xGa_1-xSb, Al_xGa_1-xSb, Al_xGa_1-xSb(As), GaN and any combination thereof.

7. The method of claim 2, wherein the dielectric bonding layer includes a material chosen from the group consisting of silicon oxide, silicon nitride, aluminum oxide and any combination thereof.

8. The method of claim 2, wherein the silicon protrusions have a width parallel to the main surface that is smaller than 20 nm.

9. The method of claim 1, wherein removing the at least upper portions of the silicon protrusions includes forming trenches having a depth substantially perpendicular to the main surface that is greater than a width of the trenches substantially parallel to the main surface by at least 150%.

10. The method of claim 1, wherein a processing temperature is kept below 600°

C.

11. A semiconductor structure comprising:

a substrate comprising a silicon substrate having a surface oriented in a {100} crystal plane and further having a notch oriented in a <

100>

direction;

a dielectric bonding layer formed on at least a portion of the surface; and

a semiconductor layer bonded to the silicon substrate by the dielectric bonding layer, wherein the semiconductor layer has a lattice constant different from a lattice constant of the silicon substrate.

12. The semiconductor structure of claim 11, wherein the semiconductor layer comprises a material selected from the group consisting of germanium, silicon-germanium (Si_xGe_1-x), germanium-tin (Ge_xSn_1-x), and a combination thereof.

13. The semiconductor structure of claim 12, wherein the dielectric bonding layer comprises a material chosen from the group consisting of silicon oxide, silicon nitride, aluminum oxide and a combination thereof.

14. The semiconductor structure of claim 13, wherein the substrate further comprises a recessed portion, the recessed portion comprising:

a plurality of protrusions formed in the recessed portion, wherein at least upper portions of the protrusions are formed of a III-V material; and

a plurality of shallow trench isolation (STI) structures formed adjacent to each of the protrusions.

15. The semiconductor structure of claim 14, wherein each of the protrusions extend vertically through at least portions of the adjacent STI structures to form a channel region of an n-channel transistor that protrudes above surfaces of the STI structures.

16. The semiconductor structure of claim 15, wherein the semiconductor layer comprises a patterned channel region of a p-channel transistor.

17. The semiconductor structure of claim 16, wherein at least some of the protrusions are elongated laterally in a direction parallel to the notch in the <

100>

direction.