Electronic Power Device and Method of Fabricating an Electronic Power Device

• US 20150077941A1
• Filed: 09/18/2013
• Published: 03/19/2015
• Est. Priority Date: 09/18/2013
• Status: Active Grant

• Current Assignee: Infineon Technologies Austria Ag (Infineon Technologies AG)
• Original Assignee: Infineon Technologies Austria Ag (Infineon Technologies AG)
• Inventors: Hosseini, Khalil, Mahler, Joachim, Nikitin, Ivan
• Granted Patent: US 9,420,731 B2
• Time in Patent Office: Days
• US Class Current: 361/704
• CPC Class Codes: H01L 21/4871 Bases, plates or heatsinks
• CPC Class Codes: H01L 21/4875 Connection or disconnection of other leads to or from bases or plates
• CPC Class Codes: H01L 21/4882 Assembly of heatsink parts
• CPC Class Codes: H01L 2224/06181 On opposite sides of the body
• CPC Class Codes: H01L 2224/29111 Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/29139 Silver [Ag] as principal constituent
• CPC Class Codes: H01L 2224/29144 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/29147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32245 the item being metallic
• CPC Class Codes: H01L 2224/33181 On opposite sides of the body
• CPC Class Codes: H01L 2224/8382 Diffusion bonding
• CPC Class Codes: H01L 2224/8384 Sintering
• CPC Class Codes: H01L 2224/83851 being an anisotropic conductive adhesive
• CPC Class Codes: H01L 23/3733 having a heterogeneous or anisotropic structure, e.g. powder or fibres in a matrix, wire mesh, porous structures H01L23/3732, H01L23/3737 take precedence
• CPC Class Codes: H01L 23/3735 Laminates or multilayers, e.g. direct bond copper ceramic substrates
• CPC Class Codes: H01L 23/3736 Metallic materials H01L23/3732, H01L23/3733, H01L23/3735, H01L23/3737, H01L23/3738 take precedence
• CPC Class Codes: H01L 23/49562 for devices being provided for in H01L29/00
• CPC Class Codes: H01L 23/49568 specifically adapted to facilitate heat dissipation
• CPC Class Codes: H01L 23/49844 for devices being provided for in H01L29/00
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/01032 : Germanium [Ge]
• CPC Class Codes: H01L 2924/01049 : Indium [In]
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/10272 : Silicon Carbide [SiC]
• CPC Class Codes: H01L 2924/1033 : Gallium nitride [GaN]
• CPC Class Codes: H01L 2924/13055 : Insulated gate bipolar transistor [IGBT]
• CPC Class Codes: H01L 2924/13064 : High Electron Mobility Transistor [HEMT, HFET [heterostructure FET], MODFET]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H05K 7/209 : Heat transfer by conduction from internal heat source to heat radiating structure H05K7/20909 takes precedence
• CPC Class Codes: Y10T 156/10 : Methods of surface bonding and/or assembly therefor
• CPC Class Codes: Y10T 29/49002 : Electrical device making

Abstract

An electronic device comprises a power module comprising a first main surface and a second main surface opposite to the first main surface, wherein at least a portion of the first main surface is configured as a heat dissipating surface without electrical power terminal functionality. The electronic device comprises a porous metal layer arranged on the portion of the first main surface.

Claims

1. An electronic device, comprising:

a power module comprising a first main surface and a second main surface opposite to the first main surface, wherein at least a portion of the first main surface is configured as a heat dissipating surface without electrical power terminal functionality; and

a first porous metal layer arranged on the portion of the first main surface.

2. The electronic device of claim 1, further comprising:

a second porous metal layer arranged on a portion of the second main surface, wherein at least the portion of the second main surface is configured as a heat dissipating surface without electrical power terminal functionality.

3. The electronic device of claim 1, wherein the first porous metal layer comprises a metal selected from the group consisting of Cu, Al, Ag, Ni, Mo and alloys thereof.

4. The electronic device of claim 1, wherein the first porous metal layer comprises a thickness in a range from 20 μ

m to 200 μ

m.

5. The electronic device of claim 1, wherein the first porous metal layer comprises a porosity in a range from 20% to 90%.

6. The electronic device of claim 1, wherein the first porous metal layer comprises a thermal conductivity of equal to or greater than 10 W/(mK).

7. The electronic device of claim 1, wherein the first porous metal layer is an open-celled metal foam layer.

8. The electronic device of claim 1, wherein the first porous metal layer is a particle layer comprising particles having a mean particle size in a range from 1 μ

m to 20 μ

m.

9. The electronic device of claim 1, wherein the first porous metal layer is configured to deform when the electronic device is clamped with the first porous metal layer to a first heat sink.

10. The electronic device of claim 1, further comprising:

a power semiconductor chip; and

an insulating layer extending between the power semiconductor chip and the first porous metal layer.

11. The electronic device of claim 1, wherein the power module further comprises:

a chip carrier; and

a power semiconductor chip mounted on the chip carrier, wherein the chip carrier is exposed at the portion of the first main surface of the power module.

12. The electronic device of claim 11, wherein the chip carrier comprises a metal bonded ceramic substrate or a leadframe.

13. The electronic device of claim 1, further comprising:

a first chip carrier exposed at the first main surface of the power module, and a second chip carrier exposed at the second main surface of the power module.

14. A method of manufacturing an electronic device, comprising:

providing a power module comprising a first main surface and a second main surface opposite to the first main surface, wherein the first main surface is configured as a heat dissipating surface without electrical power terminal functionality; and

forming a first porous metal layer on the first main surface.

15. The method of claim 14, wherein forming the first porous metal layer comprises:

attaching an open-celled metal foam layer to the first main surface.

16. The method of claim 14, wherein forming the first porous metal layer comprises:

depositing metal particles on the first main surface by using a cold plasma assisted particle deposition technique.

17. The method of claim 14, wherein forming the first porous metal layer comprises:

applying a metal paste on the first main surface; and

performing low-temperature sintering of the metal paste.

18. The method of claim 14, further comprising:

introducing a heat sink paste into the first porous metal layer and/or filling the first porous metal layer by galvanic deposition of a metal selected from the group consisting of Cu, Al, Ag, Ni, Mo and alloys thereof.

19. A method of mounting an electronic device to a heat sink, wherein the electronic device comprises a power module having a first main surface and a second main surface opposite to the first main surface, wherein the first main surface is configured as a heat dissipating surface without electrical power terminal functionality, and wherein a first porous metal layer is arranged on the first main surface, the method comprising:

clamping the electronic device to a first heat sink, whereby the first porous metal layer is arranged between the power module and the heat sink; and

applying a clamping pressure of equal to or more than 50 N/mm².

20. The method of claim 19, further comprising:

pre-fabricated the porous metal layer separately from the power module; and

applying the pre-fabricated porous metal layer to the first main surface before clamping the electronic device to the first heat sink.