SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

• US 20150079731A1
• Filed: 11/24/2014
• Published: 03/19/2015
• Est. Priority Date: 10/21/2009
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: YAMAZAKI, Shunpei, SUZUKI, Kunihiko, TAKAHASHI, Masahiro
• Granted Patent: US 9,679,768 B2
• Time in Patent Office: Days
• US Class Current: 438/104
• CPC Class Codes: H01L 21/02554 Oxides
• CPC Class Codes: H01L 21/02565 Oxide semiconducting materials not being Group 12/16 materials, e.g. ternary compounds
• CPC Class Codes: H01L 21/02631 Physical deposition at reduced pressure, e.g. MBE, sputtering, evaporation
• CPC Class Codes: H01L 21/02664 Aftertreatments planarisation in general H01L21/304
• CPC Class Codes: H01L 23/564 Details not otherwise provided for, e.g. protection against moisture getters H01L23/26
• CPC Class Codes: H01L 29/4908 for thin film semiconductor, e.g. gate of TFT
• CPC Class Codes: H01L 29/66969 of devices having semiconductor bodies not comprising group 14 or group 13/15 materials comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials, comprising cuprous oxide or cuprous iodide H01L21/02365
• CPC Class Codes: H01L 29/78606 with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device H01L29/78642, H01L29/78645 take precedence
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

An object is to provide a semiconductor device with stable electric characteristics in which an oxide semiconductor is used. An impurity such as hydrogen or moisture (e.g., a hydrogen atom or a compound containing a hydrogen atom such as H₂O) is eliminated from an oxide semiconductor layer with use of a halogen element typified by fluorine or chlorine, so that the impurity concentration in the oxide semiconductor layer is reduced. A gate insulating layer and/or an insulating layer provided in contact with the oxide semiconductor layer can be formed to contain a halogen element. In addition, a halogen element may be attached to the oxide semiconductor layer through plasma treatment under an atmosphere of a gas containing a halogen element.

Claims

1. A method of manufacturing a semiconductor device comprising the steps of:

forming a first oxide insulating layer over a gate electrode;

forming an oxide semiconductor layer over the first oxide insulating layer, wherein the oxide semiconductor layer overlaps with the gate electrode;

forming a second oxide insulating layer over the oxide semiconductor layer, the second oxide insulating layer containing a halogen element; and

heating the oxide semiconductor layer to remove hydrogen from the oxide semiconductor layer at least partly after forming the second oxide insulating layer.

2. The method according to claim 1, wherein at least part of hydrogen atoms contained in the oxide semiconductor layer is diffused into the second oxide insulating layer by the step of heating.

3. The method according to claim 1, wherein the step of heating is performed for suppressing generation of parasitic channel at an upper surface of the oxide semiconductor layer.

4. The method according to claim 1, wherein the halogen element is added during deposition of the second oxide insulating layer.

5. The method according to claim 1, wherein the oxide semiconductor layer is in contact with the second oxide insulating layer.

6. The method according to claim 1, wherein the oxide semiconductor layer contains hydrogen at a concentration of 5×

10¹⁹ atoms/cm³ or lower.

7. The method according to claim 1, wherein the second oxide insulating layer contains the halogen element at a concentration of 5×

10¹⁸ atoms/cm³ or higher.

8. The method according to claim 1, wherein the oxide semiconductor layer is non-single crystalline.

9. The method according to claim 1, wherein the step of heating is performed at a temperature of 100°

C. to 400°

C.

10. A method of manufacturing a semiconductor device comprising the steps of:

forming a first oxide insulating layer over a gate electrode;

forming an oxide semiconductor layer over the first oxide insulating layer, wherein the oxide semiconductor layer overlaps with the gate electrode;

forming a second oxide insulating layer over the oxide semiconductor layer;

forming a silicon nitride layer over the second oxide insulating layer; and

heating the oxide semiconductor layer at a temperature of 100°

C. or higher,

wherein the second oxide insulating layer contains fluorine.

11. The method according to claim 10, wherein fluorine is added to the second oxide insulating layer after forming the second oxide insulating layer.

12. The method according to claim 10, wherein fluorine is added to the second oxide insulating layer during forming the second oxide insulating layer.

13. The method according to claim 10, wherein at least part of hydrogen atoms contained in the oxide semiconductor layer is diffused into the second oxide insulating layer by the step of heating.

14. The method according to claim 10, wherein the oxide semiconductor layer contains hydrogen at a concentration of 5×

10¹⁹ atoms/cm³ or lower.

15. The method according to claim 10, wherein the second oxide insulating layer contains fluorine at a concentration of 5×

10¹⁸ atoms/cm³ or higher.

16. The method according to claim 10, wherein the oxide semiconductor layer is non-single crystalline.

17. A method of manufacturing a semiconductor device comprising the steps of:

forming an oxide semiconductor layer over a substrate;

forming an oxide insulating layer on the oxide semiconductor layer;

adding fluorine to the oxide insulating layer; and

performing a heat treatment after the step of adding fluorine at a temperature of 100°

C. or higher.

18. The method according to claim 17, wherein at least part of hydrogen atoms contained in the oxide semiconductor layer is diffused into the oxide insulating layer by the heat treatment

19. The method according to claim 17, wherein the heat treatment is performed for suppressing generation of parasitic channel at an upper surface of the oxide semiconductor layer.

20. The method according to claim 17, wherein the oxide semiconductor layer contains hydrogen at a concentration of 5×

10¹⁹ atoms/cm³ or lower.

21. The method according to claim 17, wherein the oxide semiconductor layer is non-single crystalline.

22. The method according to claim 17, wherein the oxide semiconductor layer has a thickness of greater than or equal to 2 nm and less than or equal to 200 nm.