TERMINATION ARRANGEMENT FOR VERTICAL MOSFET

• US 20150079749A1
• Filed: 11/24/2014
• Published: 03/19/2015
• Est. Priority Date: 05/22/2012
• Status: Active Grant

• Current Assignee: Infineon Technologies AG, Infineon Technologies Austria Ag (Infineon Technologies AG)
• Original Assignee: Infineon Technologies AG
• Inventors: WOOD, Andrew, ZUNDEL, Markus
• Granted Patent: US 9,871,119 B2
• Time in Patent Office: Days
• US Class Current: 438/270
• CPC Class Codes: H01L 21/265 producing ion implantation
• CPC Class Codes: H01L 21/28008 Making conductor-insulator-semiconductor electrodes
• CPC Class Codes: H01L 21/765 by field effect H01L21/76264 takes precedence
• CPC Class Codes: H01L 29/0661 specially adapted for altering the breakdown voltage by removing semiconductor material at, or in the neighbourhood of, a reverse biased junction, e.g. by bevelling, moat etching, depletion etching
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/423 not carrying the current to be rectified, amplified or switched
• CPC Class Codes: H01L 29/42372 characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out H01L29/42324 takes precedence
• CPC Class Codes: H01L 29/66704 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

Representative implementations of devices and techniques provide a termination arrangement for a transistor structure. The periphery of a transistor structure may include a recessed area having features arranged to improve performance of the transistor at or near breakdown.

Claims

1. A method comprising:

arranging a semiconductor layer of a transistor structure, the semiconductor layer having an active region and an adjacent termination region, the termination region including a recessed area;

forming a field insulator layer at a first portion of the recessed area of the termination region to form an insulator step structure; and

forming a gate insulator layer at a second adjacent portion of the recessed area of the termination region.

2. The method of claim 1, further comprising implanting a deep body region at the recessed area of the termination region below at least one of the field insulator layer and the gate insulator layer.

3. The method of claim 1, further comprising overlaying the insulator step structure with a field plate structure.

4. The method of claim 1, further comprising:

removing a portion of the semiconductor layer at the active region to form one or more gate trenches, the gate trenches penetrating the semiconductor layer to a depth substantially equal to a depth of the termination region; and

embedding a gate structure in each of the one or more gate trenches.

5. The method of claim 1, further comprising forming a source layer on portions of the semiconductor layer at the active region and excluding a source layer from portions of the semiconductor layer at a periphery of the active region.

6. The method of claim 2, further comprising implanting the semiconductor layer at preselected locations of the active region to form one or more deep body portions in the active region of the semiconductor layer, one or more of the deep body portions having a depth that is substantially equal to or greater than a depth of the deep body region of the termination region.

7. The method of claim 2, further comprising modifying a breakdown voltage of the transistor structure by altering a location of the insulator step structure with respect to the deep body region at the termination region.

8. The method of claim 2, further comprising changing at least one of a spatial location and a distribution of an electric field formed during an avalanche condition of the transistor structure by modifying one or more dimensions of the deep body at the termination region.

9. The method of claim 2, further comprising selecting a doping profile for the deep body region of the termination region such that an electric field produced at a breakdown voltage of the transistor structure is located substantially below a surface of the semiconductor layer at the recessed area and below the insulator step structure.

10. The method of claim 2, further comprising introducing the deep body region at the recessed area of the termination region using a masked high energy implant prior to forming mesas or trenches in the active region and/or termination region.

12. The method of claim 2, further comprising introducing the deep body region at the recessed area of the termination region using at least one of a masked implant in conjunction with a self-alignment to the insulator step structure or using a masked tilted implant in dual or quad mode, after forming mesas or trenches in the active region and/or termination region.

13. A method comprising:

arranging a semiconductor layer of a transistor structure, the semiconductor layer having an active region and an adjacent termination region, the termination region including a recessed area;

forming a field insulator layer at a first portion of the recessed area of the termination region to form an insulator step structure, the step insulator structure being formed as a thickening of the field insulator layer from a first thickness to a second thickness; and

forming a gate insulator layer at a second adjacent portion of the recessed area of the termination region.

11. The method of claim 14, further comprising introducing the deep body region at the recessed area of the termination region using a masked low energy implant after forming mesas or trenches in the active region and/or termination region.

14. The method of claim 13, further comprising overlaying the insulator step structure with a field plate structure.

15. The method of claim 13, further comprising:

removing a portion of the semiconductor layer at the active region to form one or more gate trenches, the gate trenches penetrating the semiconductor layer to a depth substantially equal to a depth of the termination region; and

embedding a gate structure in each of the one or more gate trenches.

16. The method of claim 13, further comprising modifying a breakdown voltage of the transistor structure by altering a location of the insulator step structure.

17. The method of claim 13, further comprising changing at least one of a spatial location and a distribution of an electric field formed during an avalanche condition of the transistor structure.

18. The method of claim 13, further comprising implanting a deep body region at the recessed area of the termination region below at least one of the field insulator layer and the gate insulator layer.

19. The method of claim 18, further comprising introducing the deep body region at the recessed area of the termination region using a masked high energy implant prior to forming mesas or trenches in the active region and/or termination region.

20. The method of claim 18, further comprising introducing the deep body region at the recessed area of the termination region using a masked low energy implant after forming mesas or trenches in the active region and/or termination region.

21. The method of claim 18, further comprising introducing the deep body region at the recessed area of the termination region using at least one of a masked implant in conjunction with a self-alignment to the insulator step structure or using a masked tilted implant in dual or quad mode, after forming mesas or trenches in the active region and/or termination region.