Wafer Dicing from Wafer Backside and Front Side

• US 20150079761A1
• Filed: 12/11/2013
• Published: 03/19/2015
• Est. Priority Date: 09/19/2013
• Status: Active Grant

• Current Assignee: Applied Materials Incorporated
• Original Assignee: Applied Materials Incorporated
• Inventors: Lei, Wei-Sheng, Eaton, Brad, Kumar, Ajay
• Granted Patent: US 9,224,650 B2
• Time in Patent Office: Days
• US Class Current: 438/462
• CPC Class Codes: B23K 2103/08 Non-ferrous metals or alloys
• CPC Class Codes: B23K 2103/172 wherein at least one of the layers is non-metallic
• CPC Class Codes: B23K 2103/42 Plastics B23K2103/16 takes precedence
• CPC Class Codes: B23K 2103/50 Inorganic material, e.g. metals, not provided for in B23K2103/02 – B23K2103/26
• CPC Class Codes: B23K 2103/56 semiconducting semiconducting devices B23K2101/40
• CPC Class Codes: B23K 26/32 taking account of the properties of the material involved
• CPC Class Codes: B23K 26/364 for making a groove or trench, e.g. for scribing a break initiation groove
• CPC Class Codes: B23K 26/40 taking account of the properties of the material involved
• CPC Class Codes: B23K 26/402 involving non-metallic material, e.g. isolators
• CPC Class Codes: H01L 21/3081 characterised by their composition, e.g. multilayer masks, materials
• CPC Class Codes: H01L 21/31127 Etching organic layers
• CPC Class Codes: H01L 21/3213 Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
• CPC Class Codes: H01L 21/6836 Wafer tapes, e.g. grinding or dicing support tapes adhesive tapes in general C09J7/20
• CPC Class Codes: H01L 21/78 with subsequent division of the substrate into plural individual devices cutting to change the surface-physical characteristics or shape of semiconductor bodies H01L21/304
• CPC Class Codes: H01L 2221/68327 used during dicing or grinding
• CPC Class Codes: H01L 2221/6834 used to protect an active side of a device or wafer
• CPC Class Codes: H01L 2223/54433 containing identification or tracking information
• CPC Class Codes: H01L 2223/54473 for use after dicing
• CPC Class Codes: H01L 23/544 Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps test patterns for characterising or monitoring manufacturing processes H01L22/00
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 : Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

Approaches for backside laser scribe plus front side laser scribe and plasma etch dicing of a wafer or substrate are described. For example, a method of dicing a semiconductor wafer having a plurality of integrated circuits on a front side thereof and metallization on a backside thereof involves patterning the metallization on the backside with a first laser scribing process to provide a first plurality of laser scribe lines on the backside. The method also involves forming a mask on the front side. The method also involves patterning, from the front side, the mask with a second laser scribing process to provide a patterned mask with a second plurality of scribe lines exposing regions of the semiconductor wafer between the integrated circuits, wherein the second plurality of scribe lines is aligned with the first plurality of scribe lines. The method also involves plasma etching the semiconductor wafer through the second plurality of scribe lines to singulate the integrated circuits.

Claims

1. A method of dicing a semiconductor wafer comprising a plurality of integrated circuits on a front side thereof and metallization on a backside thereof, the method comprising:

patterning the metallization on the backside with a first laser scribing process to provide a first plurality of laser scribe lines on the backside, the patterning performed without using a mask;

forming a mask on the front side;

patterning, from the front side, the mask with a second laser scribing process to provide a patterned mask and to provide a second plurality of scribe lines exposing regions of the semiconductor wafer between the integrated circuits, wherein the second plurality of scribe lines is aligned with the first plurality of scribe lines; and

plasma etching the semiconductor wafer through the second plurality of scribe lines to singulate the integrated circuits.

2. The method of claim 1, further comprising:

die marking the back side of the semiconductor wafer during the first laser scribing process.

3. The method of claim 1, wherein the first and second laser scribing processes involve using the same laser conditions.

4. The method of claim 1, wherein the first and second laser scribing processes involve using a femtosecond-based laser.

5. The method of claim 1, wherein the first plurality of scribe lines comprises trenches formed partially into the backside of the semiconductor wafer.

6. The method of claim 1, wherein the second plurality of scribe lines comprises trenches formed partially into the front side of the semiconductor wafer.

7. The method of claim 1, wherein forming the mask on the front side comprises forming a water soluble mask.

8. The method of claim 1, wherein forming the mask on the front side comprises forming a UV-curable mask.

9. The method of claim 1, wherein the semiconductor wafer is a monocrystalline silicon substrate.

10-16. -16. (canceled)

17. A method of dicing a monocrystalline silicon substrate comprising a plurality of integrated circuits on a front side thereof and metallization on a backside thereof, the method comprising:

patterning the metallization on the backside of the monocrystalline silicon substrate with a first femtosecond-based laser scribing process to provide a first plurality of laser scribe lines on the backside, the patterning performed without using a mask;

forming a water soluble mask on the front side of the monocrystalline silicon substrate;

patterning, from the front side, the water soluble mask with a second femtosecond-based laser scribing process to provide a patterned water soluble mask and to provide a second plurality of scribe lines exposing regions of the monocrystalline silicon substrate between the integrated circuits, wherein the second plurality of scribe lines is aligned with the first plurality of scribe lines;

plasma etching the monocrystalline silicon substrate through the second plurality of scribe lines to singulate the integrated circuits; and

removing the patterned water soluble mask with an aqueous solution.

18. The method of claim 17, further comprising:

die marking the back side of the monocrystalline silicon substrate during the first femtosecond-based laser scribing process.

19. The method of claim 17, wherein the first and second femtosecond-based laser scribing processes involve using the same laser conditions.

20. The method of claim 17, wherein the first plurality of scribe lines comprises trenches formed partially into the backside of the monocrystalline silicon substrate, and wherein the second plurality of scribe lines comprises trenches formed partially into the front side of the monocrystalline silicon substrate.

21. A method of dicing a semiconductor wafer comprising a plurality of integrated circuits on a front side thereof and metallization on a backside thereof, the method comprising:

patterning the metallization on the backside with a first laser scribing process to provide a first plurality of laser scribe lines on the backside, and die marking the back side of the semiconductor wafer during the first laser scribing process;

forming a mask on the front side;

patterning, from the front side, the mask with a second laser scribing process to provide a patterned mask with a second plurality of scribe lines exposing regions of the semiconductor wafer between the integrated circuits, wherein the second plurality of scribe lines is aligned with the first plurality of scribe lines; and

plasma etching the semiconductor wafer through the second plurality of scribe lines to singulate the integrated circuits.

22. The method of claim 21, wherein the first and second laser scribing processes involve using the same laser conditions.

23. The method of claim 21, wherein the first and second laser scribing processes involve using a femtosecond-based laser.

24. The method of claim 21, wherein the first plurality of scribe lines comprises trenches formed partially into the backside of the semiconductor wafer.

25. The method of claim 21, wherein the second plurality of scribe lines comprises trenches formed partially into the front side of the semiconductor wafer.

26. The method of claim 21, wherein forming the mask on the front side comprises forming a water soluble mask.

27. The method of claim 21, wherein forming the mask on the front side comprises forming a UV-curable mask.