SEMICONDUCTOR DEVICE HAVING BURIED BIT LINES AND METHOD FOR FABRICATING THE SAME

• US 20150079767A1
• Filed: 11/19/2014
• Published: 03/19/2015
• Est. Priority Date: 08/28/2012
• Status: Active Grant

• Current Assignee: SK Hynix Inc.
• Original Assignee: SK Hynix Inc.
• Inventors: MYUNG, Ju-Hyun, HWANG, Eui-Seong, PARK, Eun-Shil, KIM, Tae-Yoon
• Granted Patent: US 9,443,858 B2
• Time in Patent Office: Days
• US Class Current: 438/478
• CPC Class Codes: H01L 21/2236 from or into a plasma phase
• CPC Class Codes: H01L 21/743 Making of internal connections, substrate contacts
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/41741 for vertical or pseudo-vertical devices
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence
• CPC Class Codes: H10B 12/053 the transistor being at least partially in a trench in the substrate vertical transistor in combination with a capacitor formed in a substrate trench H10B12/0383
• CPC Class Codes: H10B 12/482 Bit lines

Abstract

A semiconductor device includes semiconductor bodies formed substantially perpendicular to a semiconductor substrate, buried bit lines formed in the semiconductor bodies and including a metal silicide; and barrier layers formed under and over the buried bit lines and containing germanium.

Claims

1-8. -8. (canceled)

9. A method for fabricating a semiconductor device, comprising:

forming semiconductor bodies in which a first barrier layer, a silicon layer and a second barrier layer are stacked substantially perpendicular to a semiconductor substrate; and

forming buried bit lines by silicidating the silicon layer.

10. The method according to claim 9, wherein the first barrier layer and the second barrier layer include silicon germanium.

11. The method according to claim 10, wherein a content of germanium in the first barrier layer and a content of germanium in the second barrier layer, respectively, is at least approximately 30%.

12. The method according to claim 9, wherein the forming of the semiconductor bodies comprises:

forming a stack layer in which the first barrier layer, the silicon layer and the second barrier layer are sequentially stacked, over the semiconductor substrate; and

selectively etching the stack layer, thereby defining trenches and forming the semiconductor bodies with both sidewalls, which are separated from one another by the trenches.

13. The method according to claim 9, wherein the first barrier layer, the silicon layer and the second barrier layer are formed through epitaxial growth.

14. The method according to claim 9, wherein the forming of the buried bit lines comprises:

forming a passivation layer that covers sidewalls of the semiconductor bodies, to expose sidewalls of the silicon layer;

forming a metal-containing layer over entire surfaces of the semiconductor bodies including the passivation layer;

forming a metal silicide layer by reacting the silicon layer and the metal-containing layer with each other through annealing; and

removing the portion of the metal-containing layer, which is not reacted.

15. The method according to claim 9, wherein the buried bit lines comprise a cobalt silicide.

16. A method for fabricating a semiconductor device, comprising:

forming a stack layer in which a first germanium-containing layer, a first silicon layer, a second germanium-containing layer and a second silicon layer are sequentially stacked, over a silicon substrate;

selectively etching the stack layer, thereby defining trenches and forming semiconductor bodies with both sidewalls, which are separated from one another by the trenches;

forming a passivation layer that covers sidewalls of the semiconductor bodies, to expose sidewalls of the first silicon layer;

forming buried bit lines by silicidating the first silicon layer; and

etching the second silicon layer, thereby forming a plurality of semiconductor pillars that includes channel regions of vertical channel transistors.

17. The method according to claim 16, further comprising:

forming storages that are connected with the plurality of semiconductor pillars.

18. The method according to claim 16, wherein the first germanium-containing layer and the second germanium-containing layer include of silicon germanium.

19. The method according to claim 18, wherein a content of germanium in the first germanium-containing layer and a content of germanium in the second germanium-containing layer, respectively, is at least approximately 30%.

20. The method according to claim 16, wherein the first germanium-containing layer, the first silicon layer, the second germanium-containing layer and the second silicon layer are formed through epitaxial growth.

21. The method according to claim 16, wherein the forming of the passivation layer comprises:

forming a first passivation layer along surfaces of structures including the semiconductor bodies;

forming a sacrificial layer to fill lower portions of the trenches;

forming a second passivation layer on both sidewalls of the semiconductor bodies including the first passivation layer;

recessing the sacrificial layer by a predetermined thickness, thereby exposing a portion of the first passivation layer formed on sidewalls of the first silicon layer; and

removing the exposed portion of the first passivation layer.

22. The method according to claim 21, wherein the sacrificial layer that fills the lower portions of the trenches is formed so that an upper surface of the sacrificial layer is positioned between an upper surface and a lower surface of the second germanium-containing layer.

23. The method according to claim 21, wherein the sacrificial layer that is recessed is formed so that an upper surface of the sacrificial layer is positioned between an upper surface and a lower surface of the first germanium-containing layer.

24. The method according to claim 16, wherein the forming of the buried bit lines comprises:

forming a metal-containing layer on surfaces of the semiconductor bodies including the passivation layer;

forming a metal silicide layer by reacting the metal-containing layer with the first silicon layer through annealing; and

removing the portion of metal-containing layer, which has not reacted.

25. The method according to claim 16, wherein the buried bit lines comprise a cobalt silicide.