ACKNOWLEDGEMENT-LESS PROTOCOL FOR SOLID STATE DRIVE INTERFACE

• US 20150081955A1
• Filed: 09/18/2014
• Published: 03/19/2015
• Est. Priority Date: 09/18/2013
• Status: Active Grant

• Current Assignee: JP Morgan Chase Bank, N.A. (JP Morgan Chase & Co)
• Original Assignee: HGST, Inc. (Western Digital Corporation)
• Inventors: VUCINIC, Dejan, GUYOT, Cyril, MATEESCU, Robert
• Granted Patent: US 9,535,870 B2
• Time in Patent Office: Days
• US Class Current: 711/103
• CPC Class Codes: G06F 13/4282 on a serial bus, e.g. I2C bus, SPI bus on daisy chain buses G06F13/4247
• CPC Class Codes: G06F 2206/1014 One time programmable [OTP] memory, e.g. PROM, WORM
• CPC Class Codes: G06F 3/061 Improving I/O performance
• CPC Class Codes: G06F 3/0613 in relation to throughput
• CPC Class Codes: G06F 3/0656 Data buffering arrangements
• CPC Class Codes: G06F 3/0659 Command handling arrangements, e.g. command buffers, queues, command scheduling
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: G06F 3/0682 Tape device
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

The present disclosure relates to methods and systems for performing operations in a communications protocol. An example method can include submitting, from a device, a request for a queue entry representing a command from a host comprising a request for data stored at a device memory location; receiving the command from the host; and executing the command. An example method can also include selecting a bit string representing whether a requested data stream has been received, and storing the bit string into a memory buffer portion to mark the buffer portion. The method can include receiving, into the memory buffer, the stream. The method can include retrieving contents of the buffer portion, and determining whether the contents contain the bit string. If so, the method can include determining that portions of the stream have not been received. Otherwise, the method can include determining that the stream has been received.

Claims

1. A method of performing operations in a communications protocol, the method comprising:

selecting a bit string for representing whether a requested data has been received, wherein the bit string is selected to differ from a pre-determined portion of the requested data;

marking the portion of the memory buffer with the selected bit string, by storing the selected bit string into a portion of a memory buffer;

receiving, into the memory buffer, the requested data;

retrieving the contents of the portion of the memory buffer;

determining whether the contents of the portion of the memory buffer contain the selected bit string;

if the contents of the portion of the memory buffer contain the selected bit string,

determining that portions of the requested data have not yet been received; and

otherwise,

determining that the requested data has been received successfully.

2. The method of claim 1, wherein storing the selected bit string into the portion of the memory buffer comprises:

segmenting the memory buffer into a plurality of portions based on a size of a transaction-layer packet (TLP) in a peripheral component interconnect express (PCIe) standard, and

storing the selected bit string into the segmented plurality of portions of the memory buffer.

3. The method of claim 1, wherein selecting the bit string comprises:

determining a size of the bit string based on a total capacity of the storage medium and on a size of an individual portion of the requested data; and

selecting a value for the bit string based on the determined size of the bit string.

4. The method of claim 3, wherein determining the size of the bit string comprises calculating a log₂ of the total capacity of the storage medium divided by the size of the individual portion of the requested data.

5. The method of claim 3, wherein the value for the bit string comprises a random bit sequence, wherein a length of the random bit sequence is based on the determined size of the bit string.

6. The method of claim 3, wherein the value for the bit string is selected during an initial power-up of at least one of a host and a storage device.

7. The method of claim 3, wherein the value for the bit string is selected upon a determination that a write operation to a storage device has invalidated a current value for the bit string.

8. The method of claim 1, wherein the communication protocol includes commands with command formats compatible with the Non-Volatile Memory Express standard.

9. The method of claim 1, further comprising requesting by a host in communication with the memory buffer the requested data.

10. The method of claim 9, wherein the communication protocol is defined between the host and a target in communication with storage for storing the requested data.

11. The method of claim 10, wherein the storage comprises at least one of a phase-change memory, magnetoresistive read only memory, and resistive read only memory.

12. A system for performing operations in a communications protocol, the system comprising:

memory in communication with a host;

a target in communication with the host via the communication protocol, for transmitting requested data;

storage, in communication with the target, for storing and retrieving the requested data; and

a processor in communication with the host, with the memory, and with the storage, the processor configured to;

select a bit string for representing whether the requested data has been received, wherein the bit string is selected to differ from a pre-determined portion of the requested data;

mark the portion of the memory buffer with the selected bit string, by storing the selected bit string into a portion of a memory buffer;

receive, into the memory buffer, the requested data;

retrieve the contents of the portion of the memory buffer;

determine whether the contents of the portion of the memory buffer contain the selected bit string;

if the contents of the portion of the memory buffer contain the selected bit string,

determine that portions of the requested data have not yet been received; and

otherwise,

determine that the requested data has been received successfully.

13. The system of claim 12, wherein processor configured to store the selected bit string into the portion of the memory buffer comprises the processor being configured to:

segment the memory buffer into a plurality of portions, wherein a size of each portion is based on a size of a transaction-layer packet (TLP) in a peripheral component interconnect express (PCIe) standard; and

store the selected bit string into the segmented plurality of portions of the memory buffer.

14. The system of claim 12, wherein the processor configured to select the bit string comprises the processor being configured to:

determine a size of the bit string based on a total capacity of the storage medium and on a size of an individual portion of the requested data; and

select a value for the bit string based on the determined size of the bit string.

15. The system of claim 14, wherein processor configured to determine the size of the bit string comprises the processor being configured to calculate a log₂ of the total capacity of the storage medium divided by the size of the individual portion of the requested data.

16. The system of claim 14, wherein the value for the bit string comprises a random bit sequence, wherein a length of the random bit sequence is based on the determined size of the bit string.

17. The system of claim 14, wherein the value for the bit string is selected during an initial power-up of at least one of a host and a storage device.

18. The system of claim 14, wherein the value for the bit string is selected upon a determination that a write operation to a storage device has invalidated a current value for the bit string.

19. The system of claim 12, wherein the communication protocol includes commands with command formats compatible with the Non-Volatile Memory Express standard.

20. The system of claim 12, wherein the storage comprises at least one of a phase-change memory, magnetoresistive read only memory, and resistive read only memory.