DYNAMIC HETEROGENEOUS HASHING FUNCTIONS IN RANGES OF SYSTEM MEMORY ADDRESSING SPACE

• US 20150082002A1
• Filed: 09/19/2013
• Published: 03/19/2015
• Est. Priority Date: 09/19/2013
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Ray, Joydeep, Parra, Jorge E., Nagarajan, Ramadass
• Granted Patent: US 9,424,209 B2
• Time in Patent Office: Days
• US Class Current: 711/216
• CPC Class Codes: G06F 12/0607 Interleaved addressing
• CPC Class Codes: G06F 13/16 for access to memory bus G06F13/28 takes precedence
• CPC Class Codes: H04L 9/3242 involving keyed hash functions, e.g. message authentication codes [MACs], CBC-MAC or HMAC

Abstract

Dynamic heterogeneous hashing function technology for balancing memory requests between multiple memory channels is described. A processor includes functional units and multiple memory channels, and a memory controller unit (MCU) coupled between them. The MCU includes a dynamic heterogeneous hashing module (DHHM) that includes multiple specific-purpose hashing function blocks that define different interleaving sequences for memory requests to alternately access the multiple memory channels. The DHHM also includes a hashing-function selection block. The hashing-function selection block is operable to identify a requesting functional unit originating a current memory request and to select one of the specific-purpose hashing function blocks for the current memory request in view of the requesting functional unit.

Claims

1. A processor comprising:

a plurality of functional units;

a plurality of memory channels coupled to a system memory; and

a memory controller unit (MCU) coupled to the plurality of functional units and the plurality of memory channels, wherein the MCU comprises a dynamic heterogeneous hashing module (DHHM) comprising;

a plurality of specific-purpose hashing function blocks that define different interleaving sequences for memory requests to alternately access the plurality of memory channels; and

a hashing-function selection block operable to identify a requesting functional unit from the plurality of functional units originating a current memory request and to select one of the plurality of specific-purpose hashing function blocks for the current memory request in view of the requesting functional unit.

2. The processor of claim 1, wherein the DHHM further comprises a general-purpose hashing function block that defines a default interleaving sequence for the memory requests to alternately access the plurality of memory channels, and wherein the hashing-function selection block is operable to select one of the plurality of specific-purpose hashing function blocks or general-purpose hashing function block for the current memory request in view of the requesting functional unit.

3. The processor of claim 2, wherein the general-purpose hashing function block is to perform a first hashing function and a first hashing function block of the plurality of special-purpose hashing function blocks is to perform a second hashing function, wherein the first hashing function is Bit6 XOR Bit13 XOR Bit 19, and wherein the second hashing function is Bit6 XOR Bit9 XOR Bit13 XOR Bit19.

4. The processor of claim 2, wherein the general-purpose hashing function block is to perform a first hashing function and a first hashing function block of the plurality of special-purpose hashing function blocks is to perform a second hashing function, wherein the first hashing function is Bit6 XOR Bit13 XOR Bit 19, and wherein the second hashing function is Bit6 XOR Bit9 XOR Bit10 XOR Bit13 XOR Bit19.

5. The processor of claim 2, wherein the hashing-function selection block comprises:

a memory address range comparator to receive a memory address of the current memory request to identify the requesting functional unit; and

a multiplexer coupled to the memory address range comparator and to receive outputs from the plurality of specific-purpose hashing function blocks and the general-purpose hashing function block as inputs to the multiplexer, wherein an output of the memory address range comparator is configured to control the multiplexer to output one of the inputs in view of the memory address of the current memory request.

6. The processor of claim 5, wherein the memory address range comparator comprises a single comparator to compare the memory address against a plurality of address ranges.

7. The processor of claim 5, wherein the memory address range comparator comprises a plurality of comparators, wherein each of the plurality of comparators is configured to compare the memory address against a single range.

8. The processor of claim 5, wherein the DHHM further comprises a bypass block operable to bypass the multiplexer.

9. The processor of claim 1, wherein the plurality of specific-purpose hashing function blocks are programmable.

10. The processor of claim 1, wherein the DHHM further comprises a plurality of configuration registers to program the plurality of specific-purpose hashing function blocks respectively.

11. The processor of claim 1, wherein memory space of the system memory is segmented into a plurality of regions and wherein the plurality of specific-purpose hashing function blocks correspond to one of the plurality of regions of the system memory.

12. A method comprising:

receiving, by a dynamic heterogeneous hashing module (DHHM) of a memory controller unit (MCU) of a processor, a current memory request to access system memory coupled to the processor via a plurality of memory channels, wherein the DHHM comprises a plurality of specific-purpose hashing function that define different interleaving sequences for memory requests to alternately access the plurality of memory channels;

identifying, by the DHHM, a requesting functional unit from a plurality of functional units of the processor that originated the current memory request; and

selecting, by the DHHM, one of the plurality of specific-purpose hashing function for the current memory request in view of the requesting functional unit.

13. The method of claim 12, further comprising selecting, by the DHHM, a general-purpose hashing function for the current memory request in view of the requesting functional unit, wherein the general-purpose hashing function defines a default interleaving sequence for the memory requests to alternately access the plurality of memory channels.

14. The method of claim 13, further comprising:

obtaining, by the DHHM, a memory address of the current memory request; and

comparing, by the DHHM, the memory address against memory ranges corresponding to the plurality of special-purpose hashing functions and general-purpose hashing function, and wherein the selecting the one of the plurality of specific-purpose hashing functions for the current memory request comprising selecting a winning hashing function in view of the comparison.

15. The method of claim 14, further comprising:

performing the plurality of specific-purpose hashing functions on the memory address of the memory request;

performing the general-purpose hashing function on the memory address of the memory request;

outputting results of the plurality of specific-purpose hashing functions and general-purpose hashing function as inputs to a multiplexer of the DHHM;

comparing, by a comparator of the DHHM, the memory address with memory ranges corresponding to the plurality of special-purpose hashing functions and general-purpose hashing function; and

selecting, by the multiplexer, one of the inputs in view of the comparison.

16. The method of claim 15, further comprising bypassing the multiplexer when a bypass block of the DHHM is enabled.

17. The method of claim 12, further comprising organizing, by the MCU, physical memory into a plurality of memory regions, each of the plurality of memory regions corresponding to one of the plurality of special-purpose hashing functions.

18. The method of claim 13, wherein the general-purpose hashing function is Bit6 XOR Bit13 XOR Bit 19, and wherein one of the plurality of special-purpose hashing functions is Bit6 XOR Bit9 XOR Bit13 XOR Bit19.

19. The method of claim 13, wherein the general-purpose hashing function is Bit6 XOR Bit13 XOR Bit 19, and wherein one of the plurality of special-purpose hashing functions is Bit6 XOR Bit9 XOR Bit10 XOR Bit13 XOR Bit19.

20. An integrated circuit comprising:

a processor core;

a memory device operable to store code memory and data memory; and

a memory controller unit (MCU) coupled between the processor core and the memory device, wherein the MCU is configured to;

load a plurality of values in configuration registers to program a plurality of specific-purpose hashing functions of a dynamic heterogeneous hashing module (DHHM);

receive a current memory request to access the memory device via a plurality of memory channels, wherein the plurality of specific-purpose hashing function define different interleaving sequences for memory requests to alternately access the plurality of memory channels;

identify a requesting functional unit from a plurality of functional units of the processor that originated the current memory request; and

select one of the plurality of specific-purpose hashing function for the current memory request in view of the requesting functional unit.

21. The integrated circuit of claim 20, wherein the DHHM comprises:

a memory address range comparator to receive a memory address of the current memory request to identify the requesting functional unit; and

a multiplexer coupled to the memory address range comparator and to receive outputs from the plurality of specific-purpose hashing function and the general-purpose hashing function as inputs to the multiplexer, wherein an output of the memory address range comparator is configured to control the multiplexer to output one of the inputs in view of the memory address of the current memory request.

22. The integrated circuit of claim 21, wherein the memory address range comparator comprises a plurality of comparators, wherein each of the plurality of comparators is configured to compare the memory address against a single range.

23. The integrated circuit of claim 21, wherein the DHHM further comprises a plurality of configuration registers to program the plurality of specific-purpose hashing functions.