FAST RECALIBRATION CIRCUITRY FOR INPUT/OUTPUT (IO) COMPENSATION FINITE STATE MACHINE POWER-DOWN-EXIT

• US 20150082011A1
• Filed: 09/16/2013
• Published: 03/19/2015
• Est. Priority Date: 09/16/2013
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Mellinger, Todd W., Denler, Nicholas J.
• Granted Patent: US 9,292,076 B2
• Time in Patent Office: Days
• US Class Current: 713/1
• CPC Class Codes: G06F 1/3243 Power saving in microcontroller unit
• CPC Class Codes: G06F 1/3287 by switching off individual functional units in the computer system
• CPC Class Codes: G11C 29/021 in voltage or current generators
• CPC Class Codes: G11C 29/022 in I/O circuitry
• CPC Class Codes: G11C 29/028 with adaption or trimming of parameters
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

Fast recalibration circuitry for input/output (IO) compensation finite state machine power-down exit is described. The fast recalibration circuitry includes a finite state machine having a volatile memory to store an IO compensation setting and a power supply coupled to the volatile memory to provide power to the volatile memory. The fast recalibration circuitry includes a persistent memory coupled to the volatile memory and one or more circuits, coupled to the volatile memory and the persistent memory, to identify an event to enter a power-down mode, wherein the power-down mode comprises the power supply removing power from the volatile memory and transfer the IO compensation setting in the volatile memory to the persistent memory prior to the power supply removing the power from the volatile memory.

Claims

1. An apparatus for input/output (IO) compensation for power-down exit comprising:

a finite state machine comprising;

a volatile memory to store an IO compensation setting;

a power supply coupled to the volatile memory to provide power to the volatile memory;

a persistent memory coupled to the volatile memory; and

one or more circuits, coupled to the volatile memory and the persistent memory, to

identify an event to enter a power-down mode, wherein the power-down mode comprises the power supply removing power from the volatile memory; and

transfer the IO compensation setting in the volatile memory to the persistent memory prior to the power supply removing the power from the volatile memory.

2. The apparatus of claim 1, further comprising one or more circuits to:

identify an event to exit the power-down mode; and

reload the IO compensation setting from the persistent memory into the finite state machine in response to the event to exit the power-down mode.

3. The apparatus of claim 2, wherein the one or more circuits comprises:

a reload register to store the IO compensation setting that is stored in the persistent memory, wherein the reload register reloads the IO compensation setting into the finite state machine in response to the event to exit the power-down mode.

4. The apparatus of claim 2, further comprising:

a digital filter circuit to remove signal noise from the IO compensation setting that is reloaded into the finite state machine, wherein the digital filter circuit performs a first set of filtering operations corresponding to the finite state machine being in a normal compensation state and the digital filter circuit performs a second set of filtering operations corresponding to the finite state machine being in a fast compensation state.

5. The apparatus of claim 2, further comprising:

a variable step circuit to adjust a step size for the IO compensation setting that is reloaded into the finite state machine, wherein the variable step circuit performs a first set of step size adjustments corresponding to the finite state machine being in a normal compensation state and the variable step circuit performs a second set of step size adjustments corresponding to the finite state machine being in a fast compensation state.

6. The apparatus of claim 1, further comprising:

a control circuit to set a compensation state of the finite state machine to one of a plurality of compensation states, wherein the plurality of compensations states comprises a fast compensation state and a normal compensation state and wherein the control circuit is further to control whether the IO compensation setting that is stored in the persistent memory is to be reloaded into the finite state machine.

7. The apparatus of claim 1, wherein the one or more circuits comprises:

a save register to store the IO compensation setting that is stored in the settings register, wherein the IO compensation setting the save register is transferred to the persistent memory.

8. The apparatus of claim 1, further comprising:

a second power supply to supply power to the persistent memory.

9. A method for input/output (IO) compensation for power-down exit comprising:

identifying an event to enter a power-down mode, wherein the power-down mode comprises a power supply removing power from a volatile memory in a finite state machine;

transferring the IO compensation setting in the volatile memory to the persistent memory prior to the power supply removing the power from the volatile memory;

identifying an event to exit the power-down mode; and

reloading the IO compensation setting from the persistent memory into the finite state machine in response to the event to exit the power-down mode.

10. The method of claim 9, wherein reloading comprises:

transferring the IO compensation setting that is stored in the persistent memory to a reload register; and

reloading the IO compensation setting from the reload register into the finite state machine in response to the event to exit the power-down mode.

11. The method of claim 9, further comprising:

setting a compensation state of the finite state machine to one of a plurality of compensation states, wherein the plurality of compensations states comprises a fast compensation state and a normal compensation state.

12. The method of claim 11, further comprising:

performing a first set of filtering operations in response to the finite state machine being in the normal compensation state; and

performing a second set of filtering operations in response to the finite state machine being in the fast compensation state.

13. The method of claim 11, further comprising:

performing a first set of step size adjustments to adjust a step size for the IO compensation setting that is reloaded into the finite state machine in response to the finite state machine being in the normal compensation state; and

performing a second set of step size adjustments to adjust the step size for the IO compensation setting that is reloaded into the finite state machine in response to the finite state machine being in the fast compensation state.

14. The method of claim 9, further comprising:

setting a control to reload the IO compensation setting that is stored in the persistent memory into the finite state machine in response to transferring the IO compensation setting in the volatile memory to the persistent memory prior to the power supply removing the power from the volatile memory.

15. A non-transitory, computer-readable storage medium including instructions that, when executed by a computing system, cause the computing system to perform operations comprising:

identifying, by a processor in the computing system, an event to enter a power-down mode, wherein the power-down mode comprises a power supply removing power from a volatile memory in a finite state machine;

transferring the IO compensation setting in the volatile memory to the persistent memory prior to the power supply removing the power from the volatile memory;

identifying an event to exit the power-down mode; and

reloading the IO compensation setting from the persistent memory into the finite state machine in response to the event to exit the power-down mode.

16. The storage medium of claim 15, wherein reloading comprises:

transferring the IO compensation setting that is stored in the persistent memory to a reload register; and

reloading the IO compensation setting from the reload register into the finite state machine in response to the event to exit the power-down mode.

17. The storage medium of claim 15, further comprising:

setting a compensation state of the finite state machine to one of a plurality of compensation states, wherein the plurality of compensations states comprises a fast compensation state and a normal compensation state.

18. The storage medium of claim 17, further comprising:

performing a first set of filtering operations in response to the finite state machine being in the normal compensation state; and

performing a second set of filtering operations in response to the finite state machine being in the fast compensation state.

19. The storage medium of claim 17, further comprising:

performing a first set of step size adjustments to adjust a step size for the IO compensation setting that is reloaded into the finite state machine in response to the finite state machine being in the normal compensation state; and

performing a second set of step size adjustments to adjust the step size for the IO compensation setting that is reloaded into the finite state machine in response to the finite state machine being in the fast compensation state.

20. The storage medium of claim 15, further comprising:

setting a control to reload the IO compensation setting that is stored in the persistent memory into the finite state machine in response to transferring the IO compensation setting in the volatile memory to the persistent memory prior to the power supply removing the power from the volatile memory.