Power Management in a Configurable Bus

• US 20150082064A1
• Filed: 09/27/2013
• Published: 03/19/2015
• Est. Priority Date: 09/17/2013
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Sinha, Rajesh Kumar
• Granted Patent: US 9,939,881 B2
• Time in Patent Office: Days
• US Class Current: 713/323
• CPC Class Codes: G06F 1/3209 Monitoring remote activity, e.g. over telephone lines or network connections
• CPC Class Codes: G06F 1/325 Power saving in peripheral device
• CPC Class Codes: G06F 1/3253 Power saving in bus
• CPC Class Codes: H04W 52/0251 using monitoring of local events, e.g. events related to user activity
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management
• CPC Class Codes: Y02D 30/70 in wireless communication networks

Abstract

A system includes a bus and a component interconnected via the bus. The component may enter a sleep mode during a period of no data transmission involving the component.

Claims

1. A system, comprising:

a bus;

a first component to send data over the bus; and

a second component, interconnected via the bus to the first component, comprising logic configured to;

receive the data from the first component;

based on a state of the bus, determine a start of a period in which no data is sent to the second component;

enter a sleep mode during the period; and

delay a transmission during a waking process associated with an end of the period.

2. The system of claim 1, where the logic is further configured to base the determination of the start of the period on a clock pause associated with the bus.

3. The system of claim 2, where the first component is configured to initiate a clock pause in response to a completion of a data transmission.

4. The system of claim 1, where the logic is configured to base the determination of the start of the period on a flow control bit sent by the first component via the bus.

5. The system of claim 4, where the flow control bit comprises a presence bit associated with a SLIMbus-compliant message.

6. The system of claim 1, where the logic is configured to change a value of a flow control bit to implement the delay.

7. The system of claim 6, where the flow control bit comprises a clear-to-send bit associated with a SLIMbus-compliant message.

8. The system of claim 1, where the logic is configured to send a negative acknowledgment to a source associated with the transmission to implement the delay.

9. The system of claim 1, where the logic is configured to inhibit creation of a data line to implement the delay.

10. A method, comprising:

determining a period in which no data is sent to a to a component over a bus;

in response to the determination, entering into a sleep mode associated with the component;

identifying an end of the period; and

in response to the identification, delaying a transmission over the bus during a waking process associated with the component.

11. The method of claim 10, where the bus comprises a configurable bus.

12. The method of claim 10, where the delaying of the transmission comprising transmitting a negative acknowledgment to a source associated with the transmission.

13. The method of claim 10, where the delaying of the transmission comprises changing a value of a bit, the bit indicating a readiness for reception.

14. The method of claim 10, where the delaying of the transmission comprises inhibiting creation of a data line between the component and a source.

15. The method of claim 14, where the inhibiting the creation of a data line comprises sending a negative acknowledgement in response to a connection establishment message from a management process associated with the bus.

16. A system, comprising:

a bus;

a first component to receive data, via the bus, with an associated consumption rate, the first component comprising a buffer; and

a second component comprising logic configured to;

send the data via a burst transmission over a first duration, the first duration based on a size of the buffer; and

enter the second component into a sleep mode for second duration, the second duration based on the first duration and the consumption rate.

17. The system of claim 16, where a data rate of the burst transmission is associated with a first clock frequency and the consumption rate is associated with a second clock frequency.

18. The system of claim 16, where the first and second durations comprise set values.

19. The system of claim 16, where the logic is further configured to end the first duration in response to an indication from the first component that the buffer has filled to a first predetermined level.

20. The system of claim 19, where the logic is further configured to end the second duration in response to an indication from the first component that the buffer has emptied to a second predetermined level.