SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING THE SAME

• US 20150084041A1
• Filed: 08/21/2014
• Published: 03/26/2015
• Est. Priority Date: 09/24/2013
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Kim, Sangsu, Hur, Sung Gi, Yang, Junggil, Yang, Changjae, Lee, Dongkyu
• Granted Patent: US 9,362,397 B2
• Time in Patent Office: Days
• US Class Current: 257/43
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/12 characterised by the materials of which they are formed
• CPC Class Codes: H01L 29/66484 with multiple gate, at least one gate being an insulated gate H01L29/66742 takes precedence
• CPC Class Codes: H01L 29/66787 with a gate at the side of the channel
• CPC Class Codes: H01L 29/775 with one dimensional charge carrier gas channel, e.g. quantum wire FET
• CPC Class Codes: H01L 29/7831 with multiple gate structure FinFETs or MuGFETs H01L29/7855, thin film transistors H01L29/78645
• CPC Class Codes: H01L 29/7832 the structure comprising a MOS gate and at least one non-MOS gate, e.g. JFET or MESFET gate
• CPC Class Codes: H10B 10/12 comprising a MOSFET load element

Abstract

A gate-all-around (GAA) semiconductor device can include a fin structure that includes alternatingly layered first and second semiconductor patterns. A source region can extend into the alternatingly layered first and second semiconductor patterns and a drain region can extend into the alternatingly layered first and second semiconductor patterns. A gate electrode can extend between the source region and the drain region and surround channel portions of the second semiconductor patterns between the source region and the drain region to define gaps between the source and drain regions. A semiconductor oxide can be on first side walls of the gap that face the source and drain regions and can be absent from at least one of second side walls of the gaps that face the second semiconductor patterns. A gate insulating layer can be on the first side walls of the gaps between the gate electrode and the semiconductor oxide.

Claims

1. A semiconductor device, comprising:

a first semiconductor pattern and a second semiconductor pattern sequentially stacked on one another on a substrate;

a gate electrode on the second semiconductor pattern extending into a gap region delimited by a sidewall of the first semiconductor pattern and a bottom surface of the second semiconductor pattern;

a gate insulating layer between the gate electrode and the first and second semiconductor patterns; and

a semiconductor oxide between the gate insulating layer and the first semiconductor pattern, the semiconductor oxide having a dielectric constant that is less than that of the gate insulating layer,

wherein the semiconductor oxide extends between the gate electrode and the substrate.

2. The device of claim 1, wherein the first semiconductor pattern comprises a material having an etch selectivity with respect to the second semiconductor pattern and has an oxidation rate that is greater than that of the second semiconductor pattern.

3. The device of claim 1, wherein the first and second semiconductor patterns each comprise a respective epitaxial layer.

4. The device of claim 1, further comprising:

a source region on a first side of the gate electrode;

a drain region on a second side of the gate electrode, wherein the source and drain regions penetrate the first and second semiconductor patterns respectively; and

wherein each of the source and drain regions comprise at least one of single crystalline semiconductor materials, conductive metal nitrides, and metals.

5. The device of claim 1, wherein the first semiconductor pattern comprises a portion between the semiconductor oxide and the substrate.

6. The device of claim 1, wherein the gate electrode has a metal gate structure including at least one of a conductive metal nitride layer and a metal layer.

7. The device of claim 1, further comprising:

a third semiconductor pattern on the second semiconductor pattern; and

a fourth semiconductor pattern on the third semiconductor pattern, the fourth semiconductor pattern penetrating the gate electrode,

wherein the third and first semiconductor patterns comprise a first material, and the fourth and second semiconductor patterns comprise a second material.

8. The device of claim 7, wherein the first semiconductor pattern is thicker than the third semiconductor pattern.

9-15. -15. (canceled)

16. A gate-all-around (GAA) semiconductor device, comprising:

a fin structure including alternatingly layered first and second semiconductor patterns;

a source region extending into the alternatingly layered first and second semiconductor patterns;

a drain region extending into the alternatingly layered first and second semiconductor patterns;

a gate electrode extending between the source region and the drain region and surrounding channel portions of the second semiconductor patterns between the source region and the drain region to define gaps between the source and drain regions;

a semiconductor oxide on first side walls of the gaps that face the source and drain regions and absent from at least one of second side walls of the gaps that face the second semiconductor patterns; and

a gate insulating layer on the first side walls of the gaps between the gate electrode and the semiconductor oxide.

17. The GAA device of claim 16 wherein the semiconductor oxide has a dielectric constant that is less than that of the gate insulating layer.

18. The GAA device of claim 16 wherein the semiconductor oxide is located on lowest one of the second side walls between the gate electrode and the substrate.

19. The GAA device of claim 16 wherein the gate insulating layer surrounds the channel portions.

20. The GAA device of claim 19 wherein the gate insulating layer contacts the channel portions.