METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE

• US 20150084049A1
• Filed: 12/03/2014
• Published: 03/26/2015
• Est. Priority Date: 06/18/2010
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: ISHIZUKA, Akihiro, YONEMITSU, Yutaka, SASAGAWA, Shinya
• Granted Patent: US 9,252,103 B2
• Time in Patent Office: Days
• US Class Current: 257/43
• CPC Class Codes: H01L 21/31111 by chemical means
• CPC Class Codes: H01L 23/535 including internal interconnections, e.g. cross-under constructions internal lead connections H01L23/481
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

An object is to provide a method for manufacturing a semiconductor device including an oxide semiconductor and having improved electric characteristics. The semiconductor device includes an oxide semiconductor film, a gate electrode overlapping the oxide semiconductor film, and a source electrode and a drain electrode electrically connected to the oxide semiconductor film. The method includes the steps of forming a first insulating film including gallium oxide over and in contact with the oxide semiconductor film; forming a second insulating film over and in contact with the first insulating film; forming a resist mask over the second insulating film; forming a contact hole by performing dry etching on the first insulating film and the second insulating film; removing the resist mask by ashing using oxygen plasma; and forming a wiring electrically connected to at least one of the gate electrode, the source electrode, and the drain electrode through the contact hole.

Claims

1. (canceled)

2. A semiconductor device comprising:

an oxide semiconductor layer comprising a channel formation region over an insulating surface;

a source electrode and a drain electrode connected to the oxide semiconductor layer;

a first layer over and in contact with the source electrode, the drain electrode, and the channel formation region;

a second layer over the first layer; and

a wiring over the second layer;

wherein the first layer comprises gallium and oxygen,

wherein the wiring is connected to the source electrode or the drain electrode through a contact hole in the first layer and the second layer, and

wherein a diameter of the contact hole in the first layer is smaller than a diameter of the contact hole in the second layer.

3. The semiconductor device according to claim 2, wherein the first layer comprises aluminum oxide.

4. The semiconductor device according to claim 2, wherein the first layer is an insulating layer comprising gallium oxide.

5. The semiconductor device according to claim 2, wherein the second layer is an insulating layer comprising silicon and at least one of oxygen and nitrogen.

6. The semiconductor device according to claim 2, wherein the second layer is over and in contact with the first layer.

7. The semiconductor device according to claim 2, further comprising a gate electrode below the oxide semiconductor layer.

8. The semiconductor device according to claim 2, further comprising a gate electrode over the oxide semiconductor layer.

9. The semiconductor device according to claim 2, wherein the contact hole includes a stepped shape.

10. The semiconductor device according to claim 2, wherein the oxide semiconductor layer comprises gallium.

11. A semiconductor device comprising:

an oxide semiconductor layer comprising a channel formation region over an insulating surface, the oxide semiconductor layer comprising indium and zinc;

a source electrode and a drain electrode connected to the oxide semiconductor layer;

a first layer over and in contact with the source electrode, the drain electrode, and the channel formation region;

a gate insulating layer over the first layer;

a gate electrode over the gate insulating layer;

a second layer over the gate electrode; and

a wiring over the second layer;

wherein the first layer comprises gallium and oxygen, and

wherein the wiring is connected to the source electrode or the drain electrode through a contact hole in the first layer and the second layer.

12. The semiconductor device according to claim 11, wherein the first layer comprises aluminum oxide.

13. The semiconductor device according to claim 11, wherein the first layer is an insulating layer comprising gallium oxide.

14. The semiconductor device according to claim 11, wherein the second layer is an insulating layer comprising silicon and at least one of oxygen and nitrogen.

15. The semiconductor device according to claim 11, wherein the second layer is over and in contact with the first layer.

16. The semiconductor device according to claim 11, wherein the contact hole includes a stepped shape.

17. The semiconductor device according to claim 11, wherein the oxide semiconductor layer comprises gallium.