BOTTOM SOURCE NMOS TRIGGERED ZENER CLAMP FOR CONFIGURING AN ULTRA-LOW VOLTAGE TRANSIENT VOLTAGE SUPPRESSOR (TVS)

• US 20150084117A1
• Filed: 09/25/2013
• Published: 03/26/2015
• Est. Priority Date: 06/17/2009
• Status: Active Grant

• Current Assignee: Alpha & Omega Semiconductor, Ltd.
• Original Assignee: Alpha & Omega Semiconductor, Ltd.
• Inventors: Bobde, Madhur
• Granted Patent: US 10,205,017 B2
• Time in Patent Office: Days
• US Class Current: 257/328
• CPC Class Codes: H01L 21/8249 Bipolar and MOS technology
• CPC Class Codes: H01L 27/0716 in combination with vertical bipolar transistors and diodes, or capacitors, or resistors
• CPC Class Codes: H01L 29/66234 Bipolar junction transistors [BJT]
• CPC Class Codes: H01L 29/6628 Inverse transistors
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/70 Bipolar devices
• CPC Class Codes: H01L 29/732 Vertical transistors
• CPC Class Codes: H01L 29/7327 Inverse vertical transistors
• CPC Class Codes: H01L 29/7804 the other device being a pn-junction diode
• CPC Class Codes: H01L 29/7808 the other device being a breakdown diode, e.g. Zener diode
• CPC Class Codes: H01L 29/781 Inverted VDMOS transistors, i.e. Source-Down VDMOS transistors
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence

Abstract

A low voltage transient voltage suppressing (TVS) device supported on a semiconductor substrate supporting an epitaxial layer to form a bottom-source metal oxide semiconductor field effect transistor (BS-MOSFET) that comprises a trench gate surrounded by a drain region encompassed in a body region disposed near a top surface of the semiconductor substrate. The drain region interfaces with the body region constituting a junction diode. The drain region on top of the epitaxial layer constituting a bipolar transistor with a top electrode disposed on the top surface of the semiconductor functioning as a drain/collector terminal and a bottom electrode disposed on a bottom surface of the semiconductor substrate functioning as a source/emitter electrode. The body regions further comprises a surface body contact region electrically connected to a body-to-source short-connection thus connecting the body region to the bottom electrode functioning as the source/emitter terminal.

Claims

1. A low voltage transient voltage suppressing (TVS) device supported on a semiconductor substrate supporting an epitaxial layer thereon, said TVS device further comprising:

a bottom-source metal oxide semiconductor field effect transistor (BS-MOSFET) comprising a planar gate disposed adjacent to a drain region encompassed in a body region disposed near a top surface of said epitaxial layer wherein said epitaxial layer and semiconductor substrate functioning as a bottom source region of said BS-MOSFET and said drain region encompassed in said body region on top of said epitaxial layer constituting a bipolar transistor with a top electrode disposed on said top surface of said semiconductor substrate functioning as a drain/collector terminal and a bottom electrode disposed on a bottom surface of said semiconductor substrate functioning as a source/emitter electrode;

said body regions being electrically connected to a body-to-source short-connection connecting said body region to said source region; and

said drain/collector terminal is connected to said drain region and wherein said gate turning on said BS-MOSFET upon application of a threshold voltage of said BS-MOSFET thus triggering said bipolar transistor for clamping and suppressing a transient voltage substantially near a threshold voltage of said BS-MOSFET.

2. The TVS device of claim 1 wherein:

said semiconductor substrate comprises a heavily doped N-type semiconductor substrate and supporting an N-type epitaxial layer thereon for disposing a bottom source N-channel MOSFET in parallel to an NPN bipolar transistor.

4. The TVS device of claim 1 wherein:

said gate having a truncated length along a third dimension of said semiconductor substrate for reducing a total area of said BS-MOSFET and increasing a total area of said bipolar transistor.

5. The TVS device of claim 1 further comprising:

a surface body contact region at the top of the body region electrically connected to a metal layer on a top surface of said semiconductor substrate functioning as said body-to-source short-connection.

6. The TVS device of claim 5 wherein:

said surface body contact region electrically connected to a highly doped contact region disposed in said epitaxial layer as a part of said body-to-source short-connection thus electrically shorting said body region to said source region.

7. The TVS device of claim 1 wherein:

said semiconductor substrate comprises a heavily doped P-type semiconductor substrate supporting a P-type epitaxial layer thereon for disposing a bottom source P-channel MOSFET in parallel to a PNP bipolar

3. The TVS device of claim wherein:

said TVS device clamps said transient voltage at a voltage below approximately three volts (3V).

8. A transient voltage suppressing (TVS) device comprising:

a bipolar transistor functioning as a Zener clamp for suppressing a transient voltage; and

a bottom source metal oxide semiconductor field effect transistor (BS-MOSFET) connected in parallel with said bipolar transistor for triggering said bipolar transistor wherein the BS-MOSFET further comprises a planar gate;

said bipolar transistor and the bottom source MOSFET are vertical devices further comprising a drain/collector terminal on the top surface and a source/emitter terminal on the bottom surface,

the bottom source MOSFET triggers the bipolar transistor upon a transient voltage event.

9. The TVS device of claim 8 further comprising:

a body-to-source short disposed on a top surface of the TVS device.

10. The TVS device of claim 8 wherein:

the drain/collector terminal is also shorted to the planar gate of said bottom

11. A method of forming a transient voltage suppressing (TVS) device) comprising:

providing an epitaxial layer supported on a semiconductor substrate;

forming a vertical bipolar transistor in the epitaxial layer and semiconductor substrate;

forming a bottom source metal-oxide-semiconductor field effect transistor (BS-MOSFET) in parallel with the bipolar transistor wherein the drain of the BS-MOSFET also serves as the collector of the bipolar transistor, the base of the BS-MOSFET also serves as the base of the bipolar transistor and the source of the BS-MOSFET also serves as the emitter of the bipolar transistor, and wherein the epitaxial layer and the semiconductor substrate act as the source of the BS-MOSFET,

such that the BS-MOSFET turns on and triggers the bipolar transistor upon a transient voltage event.

12. The method of claim 11 further comprising:

shorting the gate of the BS-MOSFET to the drain of the BS-MOSFET such that when the voltage of the drain reaches the threshold gate voltage, the BS-MOSFET turns on.

13. The method of claim 11 further comprising:

truncating the gate to adjust the ratio of the area of the bipolar transistor to the area of the BS-MOSFET.

14. The method of claim 13 wherein:

truncating the gate adjusts the current flow through the BS-MOSFET required to trigger the bipolar transistor.

15. The method of claim 11 further comprising:

selecting the resistance of the epitaxial layer in order to adjust the current flow through the BS-MOSFET required to trigger the bipolar transistor.