SEMICONDUCTOR DEVICE INCLUDING A POWER TRANSISTOR DEVICE AND BYPASS DIODE

• US 20150084118A1
• Filed: 09/20/2013
• Published: 03/26/2015
• Est. Priority Date: 09/20/2013
• Status: Active Grant

• Current Assignee: Wolfspeed, Inc.
• Original Assignee: CREE Incorporated (Wolfspeed, Inc.)
• Inventors: Van Brunt, Edward Robert, Pala, Vipindas, Cheng, Lin
• Granted Patent: US 10,600,903 B2
• Time in Patent Office: Days
• US Class Current: 257/329
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/1608 Silicon carbide
• CPC Class Codes: H01L 29/47 Schottky barrier electrodes H01L29/435 takes precedence
• CPC Class Codes: H01L 29/66068 the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
• CPC Class Codes: H01L 29/66712 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7806 the other device being a Schottky barrier diode

Abstract

A semiconductor device includes a vertical FET device and a Schottky bypass diode. The vertical FET device includes a gate contact, a source contact, and a drain contact. The gate contact and the source contact are separated from the drain contact by at least a drift layer. The Schottky bypass diode is coupled between the source contact and the drain contact and monolithically integrated adjacent to the vertical FET device such that a voltage placed between the source contact and the drain contact is distributed throughout the drift layer by the Schottky bypass diode in such a way that a voltage across each one of a plurality of P-N junctions formed between the source contact and the drain contact within the vertical FET device is prevented from exceeding a barrier voltage of the respective P-N junction.

Claims

1. A semiconductor device comprising:

a vertical FET device including a gate contact, a source contact, and a drain contact, wherein the gate contact and the source contact are separated from the drain contact by at least a drift layer; and

a bypass diode coupled between the source contact and the drain contact and monolithically integrated adjacent to the vertical FET device such that a voltage placed between the source contact and the drain contact is distributed through the drift layer by the bypass diode in such a way that a voltage across each one of a plurality of P-N junctions formed between the source contact and the drain contact in the vertical FET device is prevented from exceeding a barrier voltage of the respective P-N junction.

2. The semiconductor device of claim 1 wherein the bypass diode is a Schottky diode.

3. The semiconductor device of claim 1 wherein each one of the plurality of P-N junctions formed between the source contact and the drain contact of the vertical FET device is between about 5-15 microns from the bypass diode.

4. The semiconductor device of claim 1 wherein preventing each one of the plurality of P-N junctions from exceeding the barrier voltage of the respective P-N junction prevents the formation of stacking faults in the drift layer of the vertical FET device.

5. The semiconductor device of claim 1 wherein the vertical FET device is a metal-oxide-semiconductor field-effect transistor (MOSFET) half-cell.

6. The semiconductor device of claim 5 wherein the vertical FET device further comprises a substrate between the drain contact and the drift layer.

7. The semiconductor device of claim 6 wherein the vertical FET device further comprises:

a first junction implant on a surface of the drift layer opposite the substrate; and

a second junction implant laterally separated from the first junction implant on the surface of the drift layer opposite the substrate.

8. The semiconductor device of claim 7 wherein:

the first junction implant comprises a first deep well region, a first base region inside the first deep well region, and a first source region adjacent to the first base region inside the first deep well region; and

the second junction implant comprises a second deep well region.

9. The semiconductor device of claim 8 wherein the bypass diode comprises:

an anode on the surface of the drift layer opposite the substrate, such that the anode partially overlaps a portion of the drift layer and the second deep well junction; and

a cathode on a surface of the substrate opposite the drift layer.

10. The semiconductor device of claim 9 wherein the anode is coupled to the source contact via an input node, and the cathode is coupled to the drain contact via an output node.

11. The semiconductor device of claim 8 wherein:

the source contact is located on the surface of the drift layer opposite the substrate, such that the source contact partially overlaps a portion of the first base region and the first source region; and

the gate contact is located on top of a gate oxide layer, which is located on the surface of the drift layer opposite the substrate, such that the gate oxide layer partially overlaps and runs between a surface of the first source region and the second deep well region.

12. A semiconductor device comprising:

a vertical FET device including a gate contact, a pair of source contacts, and a drain contact, wherein the gate contact and the pair of source contacts are separated from the drain contact by at least a drift layer; and

at least two bypass diodes coupled between the pair of source contacts and the drain contact and monolithically integrated adjacent to the vertical FET device such that a voltage placed between the pair of source contacts and the drain contact is distributed through the drift layer by the at least two bypass diodes in such a way that a voltage across each one of a plurality of P-N junctions formed between the pair of source contacts and the drain contact in the vertical FET device is prevented from exceeding a barrier voltage of the respective P-N junction.

13. The semiconductor device of claim 12 wherein each one of the at least two bypass diodes is a Schottky diode.

14. The semiconductor device of claim 12 wherein each one of the plurality of P-N junctions formed between the pair of source contacts and the drain contact of the vertical FET device is between about 5-15 microns from the furthest of the at least two bypass diodes.

15. The semiconductor device of claim 12 wherein preventing each one of the plurality of P-N junctions between the pair of source contacts and the drain contact of the vertical FET device from exceeding the barrier voltage of the respective P-N junction prevents the formation of stacking faults in the drift layer of the vertical FET device.

16. The semiconductor device of claim 12 wherein the vertical FET device is a metal-oxide-semiconductor field-effect transistor (MOSFET) full-cell.

17. The semiconductor device of claim 16 wherein the vertical FET device further comprises a substrate between the drain contact and the drift layer.

18. The semiconductor device of claim 17 wherein the vertical FET device further comprises:

a first junction implant on a surface of the drift layer opposite the substrate; and

a second junction implant laterally separated from the first junction implant on the surface of the drift layer opposite the substrate.

19. The semiconductor device of claim 18 wherein the first junction implant and the second junction implant each comprise a deep well region, a base region inside the deep well region, and a source region adjacent to the base region inside the deep well region.

20. The semiconductor device of claim 19 wherein each one of the at least two bypass diodes is monolithically integrated adjacent to the first junction implant and the second junction implant, respectively, and each one of the at least two bypass diodes comprises:

an anode on the surface of the drift layer opposite the substrate, such that the anode partially overlaps a portion of the drift layer and the second deep well junction; and

a cathode on a surface of the substrate opposite the drift layer.

21. The semiconductor device of claim 20 wherein the anode is coupled to the pair of source contacts via an input node, and the cathode is coupled to the drain contact via an output node.

22. The semiconductor device of claim 19 wherein:

each of the pair of source contacts is located on the surface of the drift layer opposite the substrate, such that each of the pair of source contacts partially overlaps a portion of the respective base region and the respective source region; and

the gate contact is located on top of a gate oxide layer, which is located on the surface of the drift layer opposite the substrate, such that the gate oxide layer partially overlaps and runs between each one of the source regions.

23. A method for manufacturing a semiconductor device comprising:

providing a substrate;

growing a drift layer on a surface of the substrate;

implanting a first junction implant and a second junction implant on the surface of the drift layer opposite the substrate, such that the first junction implant is laterally separated from the second junction implant;

providing a gate contact and a source contact on the surface of the drift layer opposite the substrate;

providing a drain contact on the surface of the substrate opposite the drift layer; and

providing at least one Schottky metal contact on the surface of the drift layer opposite the substrate, the Schottky metal contact being coupled to the source contact in order to form a bypass diode between the source contact and the drain contact.

24. The method of claim 23 wherein the bypass diode is a Schottky diode.

25. The method of claim 23 wherein each one of a plurality of P-N junctions formed between the source contact and the drain contact of the vertical FET device is between about 5-15 microns from the bypass diode.

26. The method of claim 23 wherein the Schottky metal contact is placed on the surface of the drift layer such that a voltage placed between the source contact and the drain contact is distributed through the drift layer by the bypass diode in such a way that a voltage across each one of the plurality of P-N junctions formed between the source contact and the drain contact in the vertical FET device is prevented from exceeding a barrier voltage of the respective P-N junction.

27. The method of claim 26 wherein preventing each one of the plurality of P-N junctions from exceeding the barrier voltage of the respective P-N junction prevents the formation of stacking faults in the drift layer of the vertical FET device.

28. The method of claim 23 wherein:

the first junction implant comprises a first deep well region, a first base region inside the first deep well region, and a first source region adjacent to the first base region inside the first deep well region; and

the second junction implant comprises a second deep well region.

29. The method of claim 28 wherein the Schottky metal contact partially overlaps a portion of the drift layer and the second deep well region.

30. The method of claim 29 wherein:

the source contact is located on the surface of the drift layer opposite the substrate, such that the source contact partially overlaps a portion of the first base region and the first source region; and

the gate contact is located on top of a gate oxide layer, which is located on the surface of the drift layer opposite the substrate, such that the gate oxide layer partially overlaps and runs between a surface of the first source region and the second deep well region.