LAYOUT CONFIGURATIONS FOR INTEGRATING SCHOTTKY CONTACTS INTO A POWER TRANSISTOR DEVICE

• US 20150084119A1
• Filed: 09/20/2013
• Published: 03/26/2015
• Est. Priority Date: 09/20/2013
• Status: Active Grant

• Current Assignee: Wolfspeed, Inc.
• Original Assignee: CREE Incorporated (Wolfspeed, Inc.)
• Inventors: Pala, Vipindas, Van Brunt, Edward Robert, Cheng, Lin, Palmour, John Williams
• Granted Patent: US 9,318,597 B2
• Time in Patent Office: Days
• US Class Current: 257/329
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/1608 Silicon carbide
• CPC Class Codes: H01L 29/47 Schottky barrier electrodes H01L29/435 takes precedence
• CPC Class Codes: H01L 29/66068 the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
• CPC Class Codes: H01L 29/66712 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7806 the other device being a Schottky barrier diode

Abstract

A semiconductor device includes a vertical field-effect-transistor (FET) and a bypass diode. The vertical FET device includes a substrate, a drift layer formed over the substrate, a gate contact and a plurality of source contacts located on a first surface of the drift layer opposite the substrate, a drain contact located on a surface of the substrate opposite the drift layer, and a plurality of junction implants, each of the plurality of junction implants laterally separated from one another on the surface of the drift layer opposite the substrate and extending downward toward the substrate. Each of the one or more bypass diodes are formed by placing a Schottky metal contact on the first surface of the drift layer, such that each Schottky metal contact runs between two of the plurality of junction implants.

Claims

1. A semiconductor device comprising:

a vertical FET device comprising;

a substrate;

a drift layer formed over the substrate;

a plurality of junction implants, each of the plurality of junction implants laterally separated from each other one of the plurality of junction implants in the surface of the drift layer opposite the substrate and extending downwards towards the substrate; and

at least two bypass diodes, each one of the bypass diodes comprising a Schottky metal contact on the first surface of the drift layer opposite the substrate, such that each Schottky metal contact runs between two of the plurality of junction implants.

2. The semiconductor device of claim 1 wherein each one of the at least two bypass diodes is a Schottky diode.

3. The semiconductor device of claim 1 wherein the vertical FET device further comprises:

a gate contact located on a first surface of the drift layer opposite the substrate;

a plurality of source contacts located on the first surface of the drift layer opposite the substrate; and

a drain contact located on a surface of the substrate opposite the drift layer.

4. The semiconductor device of claim 3 wherein each one of a plurality of P-N junctions formed between the plurality of source contacts and the drain contact of the vertical FET device are between about 5-15 microns from one of the at least two bypass diodes.

5. The semiconductor device of claim 3 wherein the vertical FET device is a metal-oxide-semiconductor field-effect transistor (MOSFET) full-cell.

6. The semiconductor device of claim 3 wherein each one of the at least two bypass diodes distributes a voltage placed between the plurality of source contacts and the drain contact of the vertical FET device in such a way that a voltage across each one of the plurality of P-N junctions formed between the plurality of source contacts and the drain contact in the vertical FET device is prevented from exceeding a barrier voltage of the respective P-N junction.

7. The semiconductor device of claim 6 wherein preventing each one of the plurality of P-N junctions from exceeding the barrier voltage of the respective P-N junction prevents the formation of stacking faults in the drift layer of the vertical FET device.

8. The semiconductor device of claim 1 wherein:

a first one of the plurality of junction implants includes a first deep well region and a first source region; and

a second one of the plurality of junction implants includes a second deep well region and a second source region.

9. The semiconductor device of claim 8 wherein:

a third one of the plurality of junction implants includes a third deep well region, a third source region, and a first base region; and

a fourth one of the plurality of junction implants includes a fourth deep well region, a fourth source region, and a second base region.

10. The semiconductor device of claim 9 wherein:

the Schottky metal contact associated with a first one of the at least two bypass diodes runs between the first source region and the third source region; and

the Schottky metal contact associated with a second one of the at least two bypass diodes runs between the second source region and the fourth source region.

11. The semiconductor device of claim 10 wherein the vertical FET device further comprises:

a gate contact located on a first surface of the drift layer opposite the substrate;

a plurality of source contacts located on the first surface of the drift layer opposite the substrate; and

a drain contact located on a surface of the substrate opposite the drift layer.

12. The semiconductor device of claim 11 wherein the gate contact is located on top of a gate oxide layer, and the gate oxide layer runs between the first source region and the second source region, and the third source region and the fourth source region, respectively.

13. The semiconductor device of claim 12 wherein each one of the plurality of source contacts is located on top of one of the source regions of each one of the plurality of junction implants, such that each one of the source contacts is in contact with at least one of the Schottky metal contacts.

14. A method for manufacturing a semiconductor device comprising:

providing a substrate;

growing a drift layer on a surface of the substrate;

implanting a plurality of junction implants in the surface of the drift layer opposite the substrate, each of the plurality of junction implants laterally separated from one another and extending downwards towards the substrate; and

providing a plurality of Schottky metal contacts on the first surface of the drift layer, such that the Schottky metal contacts run between at least two of the plurality of junction implants.

15. The method of claim 14 wherein each one of the at least two bypass diodes is a Schottky diode.

16. The method of claim 14 further comprising:

providing a gate contact on the first surface of the drift layer;

providing a plurality of source contacts on the first surface of the drift layer; and

providing a drain contact on a surface of the substrate opposite the drift layer.

17. The method of claim 16 wherein each one of a plurality of P-N junctions formed between the plurality of source contacts and the drain contact are between about 5-15 microns from one of the at least two bypass diodes.

18. The method of claim 16 wherein the semiconductor device includes a full-cell metal-oxide-semiconductor field-effect transistor (MOSFET) formed by the substrate, the drift layer, the plurality of junction implants, the gate contact, the plurality of source contacts, and the drain contact.

19. The method of claim 16 wherein each one of the at least two bypass diodes distributes a voltage placed between the plurality of source contacts and the drain contact in such a way that a voltage across each one of the plurality of P-N junctions formed between the plurality of source contacts and the drain contact is prevented from exceeding a barrier voltage of the respective P-N junction.

20. The method of claim 18 wherein preventing each one of the plurality of P-N junctions from exceeding the barrier voltage of the respective P-N junctions prevents the formation of stacking faults in the drift layer of the vertical FET device.

21. The method of claim 14 wherein:

a first one of the plurality of junction implants includes a first deep well region and a first source region; and

a second one of the plurality of junction implants includes a second deep well region and a second source region.

22. The method of claim 20 wherein:

a third one of the plurality of junction implants includes a third deep well region, a third source region, and a first base region; and

a fourth one of the plurality of junction implants includes a fourth deep well region, a fourth source region, and a second base region.

23. The method of claim 21 wherein:

the Schottky metal contact associated with a first one of the at least two bypass diodes runs between the first source region and the third source region; and

the Schottky metal contact associated with a second one of the at least two bypass diodes runs between the second source region and the fourth source region.

24. The method of claim 22 further comprising:

providing a gate contact on the first surface of the drift layer;

providing a plurality of source contacts on the first surface of the drift layer; and

providing a drain contact on a surface of the substrate opposite the drift layer.

25. The method of claim 23 wherein the gate contact is located on top of a gate oxide layer, and the gate oxide layer runs between the first source region and the second source region, and the third source region and the fourth source region, respectively.

26. The method of claim 24 wherein each one of the plurality of source contacts is located on top of one of the source regions of each one of the plurality of junction implants, such that each one of the source contacts is in contact with at least one of the Schottky metal contacts.