LANDING PAD IN PERIPHERAL CIRCUIT FOR MAGNETIC RANDOM ACCESS MEMORY (MRAM)

• US 20150084140A1
• Filed: 09/20/2013
• Published: 03/26/2015
• Est. Priority Date: 09/20/2013
• Status: Active Grant

• Current Assignee: Avalanche Technology Incorporated
• Original Assignee: Avalanche Technology Incorporated
• Inventors: Satoh, Kimihiro, Huai, Yiming
• Granted Patent: US 9,373,663 B2
• Time in Patent Office: Days
• US Class Current: 257/421
• CPC Class Codes: H10B 61/00 Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
• CPC Class Codes: H10B 61/10 comprising components having two electrodes, e.g. diodes or MIM elements

Abstract

The present invention is directed to a memory device having a via landing pad in the peripheral circuit that minimizes the memory cell size. A device having features of the present invention comprises a peripheral circuit region and a magnetic memory cell region including at least a magnetic tunnel junction (MTJ) element. The peripheral circuit region comprises a substrate and a bottom contact formed therein; a landing pad including a first magnetic layer structure formed on top of the bottom contact and a second magnetic layer structure separated from the first magnetic layer structure by an insulating tunnel junction layer, wherein each of the insulating tunnel junction layer and the second magnetic layer structure has an opening aligned to each other; and a via partly embedded in the landing pad and directly coupled to the first magnetic layer structure through the openings.

Claims

1. A memory device including:

a memory cell region; and

a peripheral circuit region comprising;

a substrate and a bottom contact formed therein;

a landing pad formed on top of said bottom contact, said landing pad comprising a conductive layer and a degraded insulating layer, thereby allowing electric current to conduct through said landing pad; and

a via formed on top of said landing pad.

8. The device according to claim 1, wherein one of said first and second magnetic layer structures comprises an anti-ferromagnetic layer and two magnetic layers having two opposite fixed magnetization directions with a ruthenium layer interposed therebetween.

2. A memory device including:

a magnetic memory cell region including at least a magnetic tunnel junction (MTJ) element; and

a peripheral circuit region comprising;

a substrate and a bottom contact formed therein;

a landing pad formed on top of said bottom contact, said landing pad comprising a first magnetic layer structure and a second magnetic layer structure with a degraded insulating junction layer interposed therebetween, thereby allowing electric current to conduct through said landing pad; and

a via formed on top of said landing pad.

3. The device according to claim 2, wherein said degraded insulating junction layer is made of magnesium oxide (MgO).

4. The device according to claim 2, wherein said via is made of tungsten (W) or copper (Cu).

5. The device according to claim 2, wherein at least one of said first and second magnetic layer structures is made of an alloy layer comprising cobalt (Co), iron (Fe), and boron (B).

6. The device according to claim 2, wherein at least one of said first and second magnetic layer structures comprises a plurality of magnetic layers.

7. The device according to claim 2, wherein one of said first and second magnetic layer structures comprises two magnetic layers having two opposite fixed magnetization directions with a ruthenium layer interposed therebetween.

9. A memory device comprising:

a memory cell region; and

a peripheral circuit region including;

a substrate and a bottom contact formed therein;

a landing pad formed on top of said bottom contact, said landing pad including at least a conductive layer and an insulating layer thereabove with an opening; and

a via partly embedded in said landing pad and directly coupled to said conductive layer through said opening.

10. A memory device comprising:

a magnetic memory cell region including at least a magnetic tunnel junction (MTJ) element; and

a peripheral circuit region comprising;

a substrate and a bottom contact formed therein;

a landing pad comprising a first magnetic layer structure formed on top of said bottom contact and a second magnetic layer structure separated from said first magnetic layer structure by an insulating tunnel junction layer, each of said insulating tunnel junction layer and said second magnetic layer structure having an opening aligned to each other; and

a via partly embedded in said landing pad and directly coupled to said first magnetic layer structure through said openings.

11. The device according to claim 10, wherein said degraded insulating junction layer is made of magnesium oxide (MgO).

12. The device according to claim 10, wherein said via is made of tungsten (W) or copper (Cu).

13. The device according to claim 10, wherein at least one of said first and second magnetic layer structures is made of an alloy layer comprising cobalt (Co), iron (Fe), and boron (B).

14. The device according to claim 10, wherein at least one of said first and second magnetic layer structures comprises a plurality of magnetic layers.

15. The device according to claim 10, wherein one of said first and second magnetic layer structures comprises two magnetic layers having two opposite fixed magnetization directions with a ruthenium layer interposed therebetween.

16. The device according to claim 10, wherein one of said first and second magnetic layer structures comprises an anti-ferromagnetic layer and two magnetic layers having two opposite fixed magnetization directions with a ruthenium layer interposed therebetween.