SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

• US 20150084141A1
• Filed: 12/24/2013
• Published: 03/26/2015
• Est. Priority Date: 09/24/2013
• Status: Active Grant

• Current Assignee: Kioxia Corporation
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: FUJIMORI, Takeshi
• Granted Patent: US 9,252,108 B2
• Time in Patent Office: Days
• US Class Current: 257/421
• CPC Class Codes: G11C 11/16 using elements in which the storage effect is based on magnetic spin effect
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2225/0651 Wire or wire-like electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 2225/06562 at least one device in the stack being rotated or offset
• CPC Class Codes: H01L 2225/06565 the devices having the same size and there being no auxiliary carrier between the devices
• CPC Class Codes: H01L 23/552 Protection against radiation, e.g. light or electromagnetic waves
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA
• CPC Class Codes: H10B 61/00 Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
• CPC Class Codes: H10B 61/22 of the field-effect transistor [FET] type
• CPC Class Codes: H10N 50/10 Magnetoresistive devices
• CPC Class Codes: H10N 50/80 Constructional details

Abstract

According to one embodiment, a semiconductor device includes a MRAM chip including a semiconductor substrate and a memory cell array area includes magnetoresistive elements which are provided on the semiconductor substrate, and a magnetic shield layer surrounding the memory cell array area in a circumferential direction of the MRAM chip, and having a closed magnetic path.

Claims

1. A semiconductor device comprising:

an MRAM chip including a semiconductor substrate, and a memory cell array area comprising magnetoresistive elements which are provided on the semiconductor substrate; and

a magnetic shield layer surrounding the memory cell array area in a circumferential direction of the MRAM chip, and having a closed magnetic path.

2. The device of claim 1, wherein the magnetic shield layer has a closed loop structure in a first cross section which is perpendicular to a surface of the semiconductor substrate and parallel to the circumferential direction.

3. The device of claim 2, wherein the magnetoresistive elements have magnetizations which are parallel to the first cross section.

4. The device of claim 2, wherein the magnetic shield layer has an end portion in a second cross section which is perpendicular to the first cross section and parallel to the surface of the semiconductor substrate.

5. The device of claim 4, wherein the end portion of the magnetic shield layer is provided outside an end portion of the MRAM chip in the second cross section.

6. The device of claim 1, wherein the magnetic shield layer is provided outside the MRAM chip and is in contact with the MRAM chip.

7. The device of claim 6, wherein

the magnetic shield layer has an opening in which a pad of the MRAM chip is exposed, the opening being adjacent to an end portion of the MRAM chip;

and

the memory cell array area is provided inside than the pad in the MRAM chip.

8. The device of claim 1, further comprising a circuit board on which the MRAM chip is mounted.

9. The device of claim 8, wherein the magnetic shield layer comprises a first magnetic layer between a lower surface of the MRAM chip and the circuit board, and a second magnetic layer covering an upper surface and a side surface of the MRAM chip.

10. The device of claim 9, further comprising an upper chip on the MRAM chip, the upper chip including a semiconductor substrate and a memory cell array area comprising magnetoresistive elements,

wherein the magnetic shield layer comprises a third magnetic layer covering an upper surface and a side surface of the upper chip.

11. The device of claim 10, wherein a lower surface of the upper chip contacts the second magnetic layer.

12. The device of claim 11, wherein the second magnetic layer has an end portion outside an end portion of the memory cell array area of the upper chip in a direction which is parallel to a surface of the semiconductor substrate.

13. A method of manufacturing a semiconductor device, the method comprising:

forming an MRAM chip including a semiconductor substrate and a memory cell array area comprising magnetoresistive elements which are provided on the semiconductor substrate; and

forming a magnetic shield layer surrounding the memory cell array area in a circumferential direction of the MRAM chip and having a closed magnetic path by an electrolytic plating.

14. The method of claim 13, wherein the magnetic shield layer has a closed loop structure in a first cross section which is perpendicular to a surface of the semiconductor substrate and parallel to the circumferential direction.

15. The method of claim 14, wherein the magnetoresistive elements have magnetizations which are parallel to the first cross section.

16. The method of claim 14, wherein the magnetic shield layer has an end portion in a second cross section which is perpendicular to the first cross section and parallel to the surface of the semiconductor substrate.

17. The method of claim 16, wherein the end portion of the magnetic shield layer is provided outside an end portion of the MRAM chip in the second cross section.

18. The method of claim 13, wherein the magnetic shield layer is provided outside the MRAM chip and is in contact with the MRAM chip.

19. The method of claim 18, wherein

the magnetic shield layer has an opening in which a pad of the MRAM chip is exposed, the opening being adjacent to an end portion of the MRAM chip;

and

the memory cell array area is provided inside than the pad in the MRAM chip.

20. The method of claim 13, further comprising mounting the MRAM chip on a circuit board.