Multi-Chip Package and Method of Formation

• US 20150084191A1
• Filed: 12/05/2014
• Published: 03/26/2015
• Est. Priority Date: 08/01/2013
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Lin, Jing-Cheng, Yu, Chen-Hua, Hung, Jui-Pin, Yeh, Der-Chyang
• Granted Patent: US 10,163,841 B2
• Time in Patent Office: Days
• US Class Current: 257/737
• CPC Class Codes: H01L 21/561 Batch processing
• CPC Class Codes: H01L 21/568 Temporary substrate used as encapsulation process aid H01L21/4832 and H01L21/566 take precedence
• CPC Class Codes: H01L 2224/12105 Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
• CPC Class Codes: H01L 2224/13111 Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/13147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/24137 the bodies being arranged next to each other, e.g. on a common substrate
• CPC Class Codes: H01L 2224/24195 the item being a discrete passive component
• CPC Class Codes: H01L 2224/82 by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
• CPC Class Codes: H01L 2224/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 23/3128 the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/49811 Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads H01L23/49827 takes precedence
• CPC Class Codes: H01L 23/5389 the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 24/13 of an individual bump connector
• CPC Class Codes: H01L 24/14 of a plurality of bump connectors
• CPC Class Codes: H01L 24/19 Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 24/20 Structure, shape, material or disposition of high density interconnect preforms
• CPC Class Codes: H01L 24/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01029 Copper [Cu]
• CPC Class Codes: H01L 2924/01047 Silver [Ag]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/18162 : of a chip with build-up interconnect
• CPC Class Codes: H01L 2924/183 : Connection portion, e.g. seal
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19042 : being an inductor
• CPC Class Codes: H01L 2924/19043 : being a resistor
• CPC Class Codes: H01L 2924/19105 : in a side-by-side arrangement on a common die mounting substrate

Abstract

A device comprises a first semiconductor die embedded in a molding compound layer, a surface-mount device embedded in the molding compound layer, a plurality of interconnect structures formed on the molding compound layer, wherein the first semiconductor die is electrically coupled to the interconnect structures and the surface-mount device is electrically coupled to the interconnect structures through at least a metal pillar and a plurality of bumps formed on and electrically coupled to the interconnect structures.

Claims

1. A device comprising:

a first semiconductor die embedded in a molding compound layer;

a surface-mount device embedded in the molding compound layer;

a plurality of interconnect structures formed on the molding compound layer, wherein;

the first semiconductor die is electrically coupled to the interconnect structures; and

the surface-mount device is electrically coupled to the interconnect structures through at least a metal pillar; and

a plurality of bumps formed on and electrically coupled to the interconnect structures.

2. The device of claim 1, wherein:

the metal pillar is formed of solder.

3. The device of claim 1, further comprising:

a second semiconductor die embedded in the molding compound layer.

4. The device of claim 1, wherein:

the surface-mount device comprises two contacts, and wherein the contacts are electrically coupled to the bumps through a conductive channel formed by the metal pillar and the interconnect structures.

5. The device of claim 4, wherein:

the metal pillar is formed on the contact of the surface-mount device.

6. The device of claim 1, wherein:

the interconnect structure comprises a plurality of redistribution lines.

7. The device of claim 1, wherein:

the surface-mount device is selected from the group consisting of capacitors, resistors, inductors.

8. The device of claim 1, wherein:

the bumps are formed of solder, copper and any combination thereof.

9. A device comprising:

a surface-mount device and a first semiconductor die embedded in a molding compound layer, wherein;

a top surface of a first side of the surface-mount device is exposed outside the molding compound layer; and

a first metal pillar and a second metal pillar are on a second side of the surface-mount device;

a plurality of interconnect structures over the molding compound layer; and

a plurality of bumps over the interconnect structures.

10. The device of claim 9, wherein:

the interconnect structures are electronically connected to the surface-mount device through the first metal pillar and the second metal pillar.

11. The device of claim 9, further comprising:

a passivation layer over a substrate of the first semiconductor die;

a plurality of metal pads in the passivation layer;

a polymer layer over the passivation layer; and

a plurality of vias in the polymer layer.

12. The device of claim 11, wherein:

the interconnect structures are electronically connected to the first semiconductor die through the vias.

13. The device of claim 9, further comprising:

a first contact and a second contact on the second side of the surface-mount device.

14. The device of claim 13, wherein:

the first metal pillar is on and in direct contact with the first contact; and

the second metal pillar is on and in direct contact with the second contact.

15. A device comprising:

a surface-mount device, a first semiconductor die and a second semiconductor die embedded in a molding compound layer, wherein;

a top surfaces of a first side of the surface-mount device is exposed outside the molding compound layer; and

the top surface of the first side of the surface-mount device is level with a top surface of a first side of the first semiconductor die; and

a plurality of interconnect structures over the molding compound layer.

16. The device of claim 15, wherein:

the first semiconductor die and the second semiconductor die are of a same height.

17. The device of claim 15, wherein:

the top surface of the first side of the first semiconductor die is level with a top surface of a first side of the second semiconductor die.

18. The device of claim 15, further comprising:

a first metal pillar and a second metal pillar are on a second side of the surface-mount device.

19. The device of claim 18, wherein:

the interconnect structures comprise a redistribution layer electrically connected to the surface-mount device through the first metal pillar and the second metal pillar.

20. The device of claim 19, further comprising:

a plurality of under bump metallization (UBM) structures over the redistribution layer; and

a plurality of bumps over the UBM structures.