MEMORY AND MEMORY SYSTEM INCLUDING THE SAME

• US 20150085564A1
• Filed: 10/03/2014
• Published: 03/26/2015
• Est. Priority Date: 09/25/2013
• Status: Active Grant

• Current Assignee: SK Hynix Inc.
• Original Assignee: SK Hynix Inc.
• Inventors: YOON, Seok-Cheol, KIM, Bo-Yeun, PARK, Jae-Boum
• Granted Patent: US 9,396,786 B2
• Time in Patent Office: Days
• US Class Current: 365/149
• CPC Class Codes: G11C 11/40611 External triggering or timing of internal or partially internal refresh operations, e.g. auto-refresh or CAS-before-RAS triggered refresh
• CPC Class Codes: G11C 11/40615 Internal triggering or timing of refresh, e.g. hidden refresh, self refresh, pseudo-SRAMs
• CPC Class Codes: G11C 2211/4065 Low level details of refresh operations

Abstract

A memory includes a plurality of word lines each coupled to one or more memory cells, an address storage unit suitable for storing an address of a word line selected for access by a control unit among the plurality of word lines at a first time point; and the control unit suitable for sequentially refreshing the plurality of word lines in response to application of a refresh command, refreshing one or more adjacent word lines adjacent to a word line corresponding to the address stored in the address storage unit in response to every Nth application of the refresh command where N is a natural number and selecting one or more of the plurality of word lines for access, wherein the first time point is included in time section other than a refresh section in which the control unit refreshes one or more word lines in response to application of the refresh command.

Claims

1. A memory comprising:

a plurality of word lines each coupled to one or more memory cells;

an address storage unit suitable for storing an address of a word line selected for access by a control unit among the plurality of word lines at a first time point; and

the control unit suitable for sequentially refreshing the plurality of word lines in response to application of a refresh command, refreshing one or more adjacent word lines adjacent to a word line corresponding to the address stored in the address storage unit in response to every Nth application of the refresh command where N is a natural number and selecting one or more of the plurality of word lines for access,

wherein the first time point is included in time section other than a refresh section in which the control unit refreshes one or more word lines in response to application of the refresh command.

2. The memory of claim 1, wherein the address storage unit periodically stores the address of the selected word line among the plurality of word lines within a preset period.

3. The memory of claim 1, wherein the address storage unit stores the address of the selected word line among the plurality of word lines in response to every Mth application of n active command where M is a natural number.

4. The memory of claim 1, wherein the address storage unit stores the address of the selected word line among the plurality of word lines at a preset time after every Qth application of the refresh command where Q is a natural number.

5. The memory of claim 1, wherein the address storage unit stores the address of the selected word line among the plurality of word lines in response to Mth application of an active command after Qth application of the refresh command where M and Q are natural numbers.

6. The memory of claim 1, wherein the control unit activates a word line corresponding to an input address in response to application of an active command, a word line corresponding to a counting address in response to application of the refresh command and the one or more adjacent word lines in response to every Nth application of the refresh command is N times, and

wherein the counting address changes whenever the refresh command is applied.

7. The memory of claim 1, wherein the control unit comprises:

a refresh con unit suitable for activating a refresh active signal one or more times in response to application of the refresh command and a target active signal in response to every Nth application of the refresh command; and

a word line control unit suitable for activating a word line corresponding to an input address in response to application of an active command, a word line corresponding to a counting address in response to activation of the refresh active signal and the one or more adjacent word lines in response to activation of the target active signal and the refresh active signal.

8. The memory of claim 7, herein the address storage unit outputs the stored address in response to activation of the target active signal.

9. A memory comprising:

a plurality of word lines each coupled to one or more memory cells;

an address input unit suitable for receiving an address from outside;

an address counting unit suitable for performing a counting operation when a refresh command is applied and generating a counting address using the counting result;

an address storage unit suitable for storing an address of a word line selected for activation by a control unit among the plurality of word lines at a first time point; and

the control unit suitable for activating a word line corresponding to the address received by the address input unit in response to application of an active command and refreshing a word line corresponding to the counting address in response to application of the refresh command and one or more adjacent word lines adjacent to a word line corresponding to the address stored in the address storage unit in response to every Nth application of the refresh command where N is a natural number,

wherein the first time point is included in time section other than refresh section in which the control unit refreshes one or more word lines in response to application of the refresh command.

10. The memory of claim 9, wherein the address storage unit periodically stores the address of the selected word line among the plurality of word lines within a preset period.

11. The memory of claim 9, wherein the address storage unit outputs the stored address in response to every Nth application of the refresh command.

12. A memory system comprising:

a memory having a plurality of word lines each coupled to one or more memory cells and suitable for sequentially refreshing the plurality of word lines in response to application of a refresh command, selecting one or more of the plurality of word lines for access, storing an address of the selected word line among the plurality of word lines at a first time point, and refreshing one or more adjacent word lines adjacent to a word line corresponding to the stored address in response to every Nth application of the refresh command; and

a memory controller suitable for periodically applying the refresh command to the memory, wherein the first time point is included in time section other than refresh section in which one or more word lines are refreshed in response to application of the refresh command.

13. The memory system of claim 12, wherein the memory periodically stores the address of the selected word line among the plurality of word lines within a preset period.

14. The memory system of claim 12, wherein the memory controller applies one or more signals of an access command, an input address and data to the memory during an access operation and

the first time point is included in an access section in which the memory performs the access operation.

15. The memory system of claim 14, wherein the access operation comprises one or more operations of activating the selected word line among the plurality of word lines, writing data to one or more memory cells coupled to the selected word line among the plurality of word lines and reading data of the one or more memory cells coupled to the selected word line among the plurality of word lines.

16. The memory system of claim 14, wherein the memory selects a word line corresponding to the input address during the access period and refreshes a word line corresponding to a counting address in response to application of the refresh command and the one or more adjacent word lines in response to every Nth application of the refresh command, and

wherein the counting address changes whenever the refresh command is applied.

17. A memory comprising:

a plurality of cell arrays each having a plurality of word lines coupled to one or more memory cells;

an address storage unit suitable for storing an address of a word line selected for access by each of a plurality of word line control units among the plurality of word lines in each of the cell arrays at a first time point;

a refresh control unit suitable for activating plurality of refresh active signals one or more times in response to application of a refresh command and a target active signal in response to every Nth application of the refresh command where N is a natural number; and

the plurality of word line control units each suitable for sequentially refreshing the plurality of word lines of a corresponding cell array in response to application of a corresponding refresh active signal among the plurality of refresh active signals, refreshing one or more adjacent word lines adjacent to a word line corresponding to the address stored in the address storage unit in the corresponding cell array in response to every Nth application of the corresponding refresh active signal among the plurality of refresh active signals when the target active signal is activated, and selecting one or more of the plurality of word lines for access,

wherein the time point is included in time section other than refresh section in which the plurality of word line control units refresh one or more word lines in response to application of the refresh command.

18. The memory of claim 17, wherein the address storage unit periodically stores the address of the selected word line among the plurality of word lines in each of the cell arrays within a preset period.

19. The memory of claim 17, wherein each of the word line control units activates a word line corresponding to an input address in response to application of an active command and selection of the corresponding cell array, refreshes a word line corresponding to a counting address in response to application of the refresh command and activates and precharges the one or more adjacent word lines in response to every Nth application of the refresh command, and

wherein the counting address changes whenever the refresh command is applied.

20. The memory of claim 17, wherein the address storage unit sequentially outputs addresses corresponding to the plurality of cell arrays in response to every Nth application of the refresh command.

21. The memory of claim 17, wherein the plurality of word line control units sequentially activate a plurality of refresh signals whenever the refresh command is applied.

22. A memory comprising:

a plurality of word lines each coupled to one or more memory cells;

an address storage unit suitable for storing an address; and

a control unit suitable for sequentially refreshing the plurality of word lines in response to application of a refresh command which is periodically applied, refreshing one or more first adjacent word lines adjacent to a word line corresponding to the address stored in the address storage unit in response to every Nth application of the refresh command, and refreshing one or more second adjacent word lines adjacent to the first adjacent word line in response to every Mth application of the refresh command, where M≧

N.

23. The memory of claim 22, wherein when the plurality of word lines are sequentially arranged and the word line corresponding to the address stored in the address storage unit is a Kth word line among the plurality of word lines,

the one or more first adjacent word lines include one or more word lines of a (K−

1)th word line and a (K+1)th word line, and

the one or more second adjacent word lines include one or more word lines of a (K−

2)th word line and a (K+1)th word line.

24. The memory of claim 22, further comprising an address counting unit suitable for performing a counting operation when a refresh command is applied, and generating a counting address using the counting result.

25. The memory of claim 24, wherein the control unit comprises:

a refresh control unit suitable for activating a refresh active signal one or more times in response to application of the refresh command, activating a first target active signal in response to every Nth application of the refresh command, and activating a second target active signal in response to every Mth application of the refresh command; and

a word line control unit suitable for activating a word line corresponding to an input address in response to application of an active command, activating a word line corresponding to the counting address in response to application of the refresh active signal, activating the one or more first adjacent word lines in response to application of the refresh active signal in case where the first target active signal is activated, and activating the one or more second adjacent word lines in response to application of the refresh active signal in case where the second target active signal is activated.

26. The memory of claim 25, wherein the word lane control unit comprises:

an address generator suitable for receiving the address stored in the address storage unit, and generating a target address corresponding to the one or more first adjacent word lines in response to activation of the first target active signal, or generating a target address corresponding to the one or more second adjacent word lines in response to activation of the second target active signal;

an address transmitter suitable for transmitting the input address as the address signal when the active command is activated, transmitting the counting address as an address signal when the refresh active signal is activated, and transmitting the target address as the address signal when one or more signals of the first and second target active signals are activated; and

a word line controller suitable for activating a word line corresponding to the address signal when the active command or the refresh active signal is activated.

27. The memory of claim 26, wherein an address corresponding to each of the (K−

1)th word line and the (K+1)th word line has a value obtained by adding or subtracting 1 to or from the value of the address corresponding to the Kth word line, and an address corresponding to each of the (K−

2)th word line and the (K+2)th word line has a value obtained by adding or subtracting 2 to or from the value of the address corresponding to the Kth word line.

28. The memory of claim 27, wherein the address generator generates a value obtained by adding or subtracting a preset value to or from the input value, and

when the first target active signal is activated, the address generator generates a value obtained by adding or subtracting 1 to or from the input value, and when the second target active signal is activated, the address generator generates a value obtained by adding or subtracting 2 to or from the input value.

29. The memory of claim 22, wherein the address storage unit stores the address of a word line of which the active count is equal to or more than a preset count among the plurality of word lines, or stores the address of a word line of which the active frequency is equal to or more than a preset frequency among the plurality of word lines.

30. The memory of claim 22, wherein the address storage unit stores the address of a word line selected at a preset time between two adjacent refresh sections.