×

THREE-DIMENSIONAL TWO-PORT BIT CELL

  • US 20150085567A1
  • Filed: 09/23/2013
  • Published: 03/26/2015
  • Est. Priority Date: 09/23/2013
  • Status: Active Grant
First Claim
Patent Images

1. A semiconductor memory, comprising:

  • a read port array disposed on a first layer of a three-dimensional integrated circuit; and

    a bit cell array disposed on a second layer of the three-dimensional integrated circuit,wherein the second layer being vertically positioned above or below the first layer, andwherein at least one bit cell of the bit cell array is coupled to at least one read port cell of the read port array by a via extending from the first layer to the second layer.

View all claims
  • 1 Assignment
Timeline View
Assignment View
    ×
    ×