THREE-DIMENSIONAL TWO-PORT BIT CELL

• US 20150085567A1
• Filed: 09/23/2013
• Published: 03/26/2015
• Est. Priority Date: 09/23/2013
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: WANG, Li-Wen, CHEN, Yen-Huei
• Granted Patent: US 9,202,557 B2
• Time in Patent Office: Days
• US Class Current: 365/156
• CPC Class Codes: G11C 11/412 using field-effect transistors only
• CPC Class Codes: G11C 11/419 Read-write [R-W] circuits
• CPC Class Codes: G11C 5/025 Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device geometrical lay-out of the components in integrated circuits, H01L27/0207
• CPC Class Codes: G11C 8/08 Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
• CPC Class Codes: G11C 8/16 Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H10B 10/12 comprising a MOSFET load element

Abstract

A semiconductor memory includes a read port array disposed on a first layer of a three-dimensional integrated circuit and a bit cell array disposed on a second layer of the three-dimensional integrated circuit. The second layer being vertically positioned above or below the first layer. At least one bit cell of the bit cell array is coupled to at least one read port cell of the read port array by a via extending from the first layer to the second layer.

Claims

1. A semiconductor memory, comprising:

a read port array disposed on a first layer of a three-dimensional integrated circuit; and

a bit cell array disposed on a second layer of the three-dimensional integrated circuit,

wherein the second layer being vertically positioned above or below the first layer, and

wherein at least one bit cell of the bit cell array is coupled to at least one read port cell of the read port array by a via extending from the first layer to the second layer.

2. The semiconductor memory of claim 1, further comprising

a read decoder and first input/output circuitry disposed on the first layer and coupled to the read port array;

and

a write decoder and second input/output circuitry disposed on the second layer and coupled to the bit cell array.

3. The semiconductor memory of claim 1, wherein the read port array includes a plurality of read port cells arranged in rows and columns, each read port cell being coupled to at least one read word line and to at least one global read bit line.

4. The semiconductor memory of claim 3, wherein each read port cell includes at least one of a tri-state buffer or a transmission gate.

5. The semiconductor memory of claim 3, wherein each read port cell includes:

a first transistor of a first type having a source coupled to a first voltage supply node and a gate coupled to a bit cell by a via extending from the first layer to the second layer;

a second transistor of the first type having a source coupled to a drain of the first transistor of the first type, a drain coupled to a global read bit line, and a gate coupled to a complementary read word line;

a first transistor of a second type having a source coupled to a second voltage supply node and a gate coupled to the bit cell by the via; and

a second transistor of the second type having a source coupled to a drain of the first transistor of the second type, a drain coupled to the global read bit line, and a gate coupled to a complementary read word line.

6. The semiconductor memory of claim 3, wherein each read port cell includes

a first transistor of a first type having a source coupled to a bit cell by a via extending from the first layer to the second layer, a gate coupled to a complementary read word line, and a drain coupled to a global read bit line;

and

a first transistor of a second type having a source coupled to the bit cell by a via extending from the first layer to the second layer, a gate coupled to a complementary read word line, and a drain coupled to the global read bit line.

7. The semiconductor memory of claim 1, wherein each bit cell of the bit cell array includes:

first and second pass transistors each coupled to a latch, to a write word line, and to a respective complementary bit line, at least one of the read pass transistors being coupled to a read port cell by a via extending from the first layer to the second layer.

8. A semiconductor memory, comprising:

a first layer of a three-dimensional integrated circuit including

read input/output circuitry,

a read decoder, and

a read port array including a plurality of read port cells arranged in rows and columns, each row of read port cells coupled to the read decoder by at least one read word line, and each column of read port cells coupled to the read input/output circuitry by a global bit line; and

a second layer of the three-dimensional integrated circuit disposed vertically above or below the first layer, the second layer including

write input/output circuitry,

a write decoder, and

a bit cell array including a plurality of read port cells arranged in rows and columns, each row of bit cells coupled to the write decoder by a write word line, and each column of bit cells coupled to the write input/output circuitry by a pair of complementary bit lines,

wherein each bit cell is coupled to a respective read port cell by a via extending from the first layer to the second layer.

9. The semiconductor memory of claim 8, wherein each of the plurality of read port cells includes at least one of a tri-state buffer or a transmission gate.

10. The semiconductor memory of claim 8, wherein each read port cell includes:

a first transistor of a first type having a source coupled to a first voltage supply node and a gate coupled to a bit cell by a via extending from the first layer to the second layer;

a second transistor of the first type having a source coupled to a drain of the first transistor of the first type, a drain coupled to a global read bit line, and a gate coupled to a complementary read word line;

a first transistor of a second type having a source coupled to a second voltage supply node and a gate coupled to the bit cell by the via; and

a second transistor of the second type having a source coupled to a drain of the first transistor of the second type, a drain coupled to the global read bit line, and a gate coupled to a complementary read word line.

11. The semiconductor memory of claim 8, wherein each read port cell includes

a first transistor of a first type having a source coupled to a bit cell by a via extending from the first layer to the second layer, a gate coupled to a complementary read word line, and a drain coupled to a global read bit line;

and

a first transistor of a second type having a source coupled to the bit cell by a via extending from the first layer to the second layer, a gate coupled to a complementary read word line, and a drain coupled to the global read bit line.

12. The semiconductor memory of claim 8, wherein each bit cell of the bit cell array includes:

first and second pass transistors each coupled to a latch, to a write word line, and to a respective complementary bit line, at least one of the read pass transistors being coupled to a read port cell by a via extending from the first layer to the second layer.

13. The semiconductor memory of claim 12, wherein each latch includes a first transistor of a first type coupled to a first transistor of a second type.

14. The semiconductor memory of claim 8, wherein the via is an inter-layer via.

15. A method, comprising:

forming circuitry on a first layer, the circuitry on the first layer including a read port array comprising a plurality of read port cells;

forming circuitry on a second layer, the circuitry on the second layer including a bit cell array comprising a plurality of bit cells; and

coupling a read port cell on the first layer to a respective bit cell on the second layer.

16. The method of claim 15, wherein forming circuitry on the first layer includes forming a read decoder and read input/output circuitry on the first layer such that the read decoder and the read input/output circuitry are coupled to the read port array.

17. The method of claim 16, wherein the read decoder is coupled to rows of bit cells by read word lines and the read input/output circuitry is coupled to columns of read bit cells by global read bit lines.

18. The method of claim 15, wherein forming circuitry on the second layer includes forming a write decoder and write input/output circuitry on the second layer such that the write decoder and the write input/output circuitry are coupled to the bit cell array.

19. The method of claim 18, wherein the write decoder is coupled to rows of bit cells by write word lines and the write input/output circuitry is coupled to columns of bit cells by bit lines.

20. The method of claim 15, wherein coupling the read port cell to a respective bit cell includes forming a via from the first layer to the second layer.