DATA MOVEMENT IN MEMORY DEVICES

• US 20150085589A1
• Filed: 09/26/2013
• Published: 03/26/2015
• Est. Priority Date: 09/26/2013
• Status: Active Grant

• Current Assignee: Tahoe Research Limited (f/k/a Learndale Limited) (Vector Capital Corporation)
• Original Assignee: Intel Corporation
• Inventors: Lu, Shih-Lien, Lin, Ying-Chen, Yang, Chia-Lin
• Granted Patent: US 9,536,577 B2
• Time in Patent Office: Days
• US Class Current: 365/189.17
• CPC Class Codes: G11C 7/065 Differential amplifiers of latching type
• CPC Class Codes: G11C 7/08 Control thereof
• CPC Class Codes: G11C 7/1045 Read-write mode select circuits

Abstract

Apparatus, systems, and methods for data movement in a memory device are described. In one embodiment, a memory controller comprises logic to move a row of data from a first row of a memory in a first section of a memory device to a second row of memory in a second section of the memory device without passing the data through a communication interface. Other embodiments are also disclosed and claimed.

Claims

1. A controller comprising logic to:

move a row of data from a first row of a memory in a first section of a memory device to a second row of memory in a second section of the memory device without passing the data through a communication interface.

2. The controller of claim 1, further comprising logic to:

move a first portion of data from the first row of data into a first set of sense amplifiers and a second portion of data from the first row of data into a second set of sense amplifiers.

3. The controller of claim 2, further comprising logic to:

move the first portion of data from the first set of sense amplifiers to a first buffer row comprising a plurality of memory cells, wherein the memory cells in the first buffer row are coupled to two adjacent bit lines; and

move the second portion of data from the second set of sense amplifiers to a second buffer row comprising a plurality of memory cells, wherein the memory cells in the second buffer row are coupled to two adjacent bit lines.

4. The controller of claim 3, further comprising logic to:

move the second portion of data from the second buffer row to a third set of sense amplifiers; and

move the first portion of data from the first buffer row to the second set of sense amplifiers.

5. The controller of claim 4, further comprising logic to:

move the first portion of data from the second set of sense amplifiers to the second row in the second section of the memory device; and

move the second portion of data from the third set of sense amplifiers to the second row in the second section of the memory device.

6. The controller of claim 1, further comprising logic to:

receive a read command to read the data from the second row; and

return, in response to the read command, a complement of the data from the second row.

7. A memory device, comprising:

at least one memory chip comprising a plurality of rows of memory cells organized into a plurality of sections;

a controller coupled to the at least one memory chip and comprising logic to;

move a row of data from a first row of a memory in a first section of a memory device to a second row of memory in a second section of the memory device without passing the data through a communication interface.

8. The memory device of claim 7, wherein the controller further comprises logic to:

move a first portion of data from the first row of data into a first set of sense amplifiers and a second portion of data from the first row of data into a second set of sense amplifiers.

9. The memory device of claim 8, wherein the controller further comprises logic to:

move the first portion of data from the first set of sense amplifiers to a first buffer row comprising a plurality of memory cells, wherein the memory cells in the first buffer row are coupled to two adjacent bit lines; and

move the second portion of data from the second set of sense amplifiers to a second buffer row comprising a plurality of memory cells, wherein the memory cells in the second buffer row are coupled to two adjacent bit lines.

10. The memory device of claim 9, wherein the controller further comprises logic to:

move the second portion of data from the second buffer row to a third set of sense amplifiers; and

move the first portion of data from the first buffer row to the second set of sense amplifiers.

11. The memory device of claim 10, wherein the controller further comprises logic to:

move the first portion of data from the second set of sense amplifiers to the second row in the second section of the memory device; and

move the second portion of data from the third set of sense amplifiers to the second row in the second section of the memory device.

12. The memory device of claim 7, wherein the controller further comprises logic to:

receive a read command to read the data from the second row; and

return, in response to the read command, a complement of the data from the second row.

13. An electronic device, comprising:

at least one electronic component; and

a memory device, comprising;

at least one memory chip comprising a plurality of rows of memory cells;

a controller coupled to the at least one memory chip and comprising logic to;

move a row of data from a first row of a memory in a first section of a memory device to a second row of memory in a second section of the memory device without passing the data through a communication interface.

14. The electronic device of claim 13, wherein the controller further comprises logic to:

move a first portion of data from the first row of data into a first set of sense amplifiers and a second portion of data from the first row of data into a second set of sense amplifiers.

15. The electronic device of claim 14, wherein the controller further comprises logic to:

move the first portion of data from the first set of sense amplifiers to a first buffer row comprising a plurality of memory cells, wherein the memory cells in the first buffer row are coupled to two adjacent bit lines; and

move the second portion of data from the second set of sense amplifiers to a second buffer row comprising a plurality of memory cells, wherein the memory cells in the second buffer row are coupled to two adjacent bit lines.

16. The electronic device of claim 15, wherein the controller further comprises logic to:

move the second portion of data from the second buffer row to a third set of sense amplifiers; and

move the first portion of data from the first buffer row to the second set of sense amplifiers.

17. The electronic device of claim 16, wherein the controller further comprises logic to:

move the first portion of data from the second set of sense amplifiers to the second row in the second section of the memory device; and

move the second portion of data from the third set of sense amplifiers to the second row in the second section of the memory device.

18. The electronic device of claim 13, wherein the controller further comprises logic to:

receive a read command to read the data from the second row; and

return, in response to the read command, a complement of the data from the second row.

19. A method, comprising:

moving a row of data from a first row of a memory in a first section of a memory device to a second row of memory in a second section of the memory device without passing the data through a communication interface.

20. The method of claim 19, further comprising:

moving a first portion of data from the first row of data into a first set of sense amplifiers and a second portion of data from the first row of data into a second set of sense amplifiers.

21. The method of claim 20, further comprising:

moving the first portion of data from the first set of sense amplifiers to a first buffer row comprising a plurality of memory cells, wherein the memory cells in the first buffer row are coupled to two adjacent bit lines; and

moving the second portion of data from the second set of sense amplifiers to a second buffer row comprising a plurality of memory cells, wherein the memory cells in the second buffer row are coupled to two adjacent bit lines.

22. The method of claim 21, further comprising:

moving the second portion of data from the second buffer row to a third set of sense amplifiers; and

moving the first portion of data from the first buffer row to the second set of sense amplifiers.

23. The method of claim 21, further comprising logic to:

moving the first portion of data from the second set of sense amplifiers to the second row in the second section of the memory device; and

moving the second portion of data from the third set of sense amplifiers to the second row in the second section of the memory device.

24. The method of claim 19, further comprising:

receiving a read command to read the data from the second row; and

returning, in response to the read command, a complement of the data from the second row.