APPLICATION SPECIFIC INTEGRATED CIRCUIT WITH COLUMN-ROW-PARALLEL ARCHITECTURE FOR ULTRASONIC IMAGING

• US 20150087991A1
• Filed: 09/25/2014
• Published: 03/26/2015
• Est. Priority Date: 09/25/2013
• Status: Active Grant

• Current Assignee: Massachusetts Institute of Technology
• Original Assignee: Massachusetts Institute of Technology
• Inventors: Chen, Kailiang, Sodini, Charles G.
• Granted Patent: US 10,806,431 B2
• Time in Patent Office: Days
• US Class Current: 600/459
• CPC Class Codes: A61B 8/13 Tomography A61B8/10, A61B8/12 take precedence; tomography for radiation diagnosis A61B6/02
• CPC Class Codes: A61B 8/4488 the transducer being a phased array
• CPC Class Codes: A61B 8/483 involving the acquisition of a 3D volume of data
• CPC Class Codes: A61B 8/54 Control of the diagnostic device
• CPC Class Codes: B06B 1/0207 Driving circuits specially adapted for particular applications, see the relevant subclass, e.g. G01; circuits for steering transducer arrays G10K11/34; basic circuits H03
• CPC Class Codes: B06B 1/0215 for generating pulses, e.g. bursts of oscillations, envelopes
• CPC Class Codes: B06B 2201/20 Application to multi-element transducer
• CPC Class Codes: B06B 2201/51 Electrostatic transducer
• CPC Class Codes: B06B 2201/55 Piezoelectric transducer
• CPC Class Codes: B06B 2201/76 Medical, dental
• CPC Class Codes: G01S 15/8925 the array being a two-dimensional transducer configuration, i.e. matrix or orthogonal linear arrays
• CPC Class Codes: G01S 15/8993 Three dimensional imaging systems
• CPC Class Codes: G01S 15/8995 Combining images from different aspect angles, e.g. spatial compounding
• CPC Class Codes: G01S 7/5202 for pulse systems
• CPC Class Codes: G01S 7/52025 for pulse systems G01S7/52034 takes precedence
• CPC Class Codes: G01S 7/52033 Gain control of receivers for seismic signals G01V1/245
• CPC Class Codes: G01S 7/5208 with integration of processing functions inside probe or scanhead
• CPC Class Codes: G10K 11/346 using phase variation
• CPC Class Codes: H03F 2200/375 Circuitry to compensate the offset being present in an amplifier
• CPC Class Codes: H03F 2203/45224 One output of the differential amplifier being taken into consideration
• CPC Class Codes: H03F 3/45076 : characterised by the way of implementation of the active amplifying circuit in the differential amplifier

Abstract

An ultrasonic imaging system is described in which a column-row-parallel architecture is provided at the circuit level of an ultrasonic transceiver. The ultrasonic imaging system can include a N×M array of transducer elements and a plurality of transceiver circuits where each transceiver circuit is connected to a corresponding one transducer element of the N×M array of transducer elements. A shared pulser gate driver and a shared VGA is provided for each row and column. Selection logic includes row select, column select, and per-element bit select. Through the column-row-parallel architecture, a variety of aperture configurations can be achieved.

Claims

1. An ultrasonic imaging system, comprising:

a N×

M array of transducer elements; and

a plurality of transceiver circuits, each transceiver circuit being connected to a corresponding one transducer element of the N×

M array of transducer elements.

2. The system of claim 1, wherein the array of transducer elements are provided on a transducer chip stacked on an application specific integrated circuit (ASIC) chip.

3. The system of claim 1, wherein each transceiver circuit comprises:

a transmitter pulser circuit connected to the transceiver circuit'"'"'s corresponding one transducer element;

a receiver low noise amplifier (LNA) selectively connected to the transceiver circuit'"'"'s corresponding one transducer element; and

a per-element selection logic receiving a row selection signal, a column selection signal, and an enable signal to control operation of the transceiver circuit.

4. The system of claim 3, further comprising:

a column gate driver connected to the transmitter pulser circuit of each transceiver circuit of a column of transceiver circuits, a total of N column gate drivers being provided;

a row gate driver connected to the transmitter pulser circuit of each transceiver circuit of a row of transceiver circuits intersecting with the column of transceiver circuits, a total of M row gate drivers being provided;

a column variable gain amplifier (VGA) buffer connected to the receiver LNA of each transceiver circuit of the column of transceiver circuits, a total of N column VGA buffers being provided; and

a row VGA buffer connected to the receiver LNA of each transceiver circuit of the row of transceiver circuits, a total of M row VGA buffers being provided.

5. The system of claim 4, wherein M=N, the system further comprising:

selection logic that connects the 2N total number of the column gate drivers and the row gate drivers to a total of N input/output ports.

6. The system of claim 4, wherein the column VGA buffer and the row VGA buffer each comprise:

a differential amplifier; and

a cancelation loop buffer connected to receive at least an output of the differential amplifier and output a cancelation loop signal at the output of the differential amplifier.

7. The system of claim 4, wherein the column VGA buffer and the row VGA buffer each comprise:

a differential amplifier; and

a cancelation loop buffer connected to receive at least an output of the differential amplifier and output a cancelation loop signal to a VGA input of the differential amplifier at an output of a corresponding LNA.

8. The system of claim 4, further comprising:

at least one analog-to-digital converter (ADC);

at least one digital-to-analog converter (DAC); and

a cancelation loop for each column VGA buffer and row VGA buffer, the cancelation loop connecting a VGA output to the ADC and feeding back a digitized output from the ADC through the DAC to a VGA input at an output of a corresponding receiver LNA.

9. The system of claim 1, further comprising:

a row-select and column-select control logic connected to the plurality of transceiver circuits for selecting at least one row and at least one column according to a selection program; and

at least one register bank connected to the row-select and column-select control logic to store the selection program.

10. The system of claim 9, wherein each transceiver circuit of the plurality of transceiver circuits comprises a per-element selection logic receiving a row selection signal, a column selection signal, and an enable signal to control operation of the transceiver circuit;

the system further comprising;

an enable select logic chain connected to the per-element selection logic for the plurality of transceiver circuits to provide the enable signal for each transceiver circuit; and

at least one extended register bank connected to one end of the enable select logic chain to shift an enable program through the enable select logic chain.

11. The system of claim 10, wherein the per-element selection logic provides selective element activation at a per-element level to form arbitrary transmit or receive apertures according to the enable program.

12. The system of claim 1, further comprising:

a total of N column gate drivers, each column gate driver connected to a corresponding row of transceiver circuits;

a total of M row gate drivers, each row gate driver connected to a corresponding row of transceiver circuits,

a total of N column variable gain amplifier (VGA) buffers, each column VGA buffer connected to a corresponding column of transceiver circuits; and

a total of M row VGA buffers, each row VGA buffer connected to a corresponding row of transceiver circuits.

13. The system of claim 12, wherein each transceiver circuit comprises:

a transmitter pulser circuit connected to the transceiver circuit'"'"'s corresponding one transducer element, selectively connected to a column-shared column gate driver of the N column gate drivers, and selectively connected to a row-shared row gate driver of the M row gate drivers;

a receiver low noise amplifier (LNA) selectively connected to the transceiver circuit'"'"'s corresponding one transducer element, selectively connected to a column-shared column VGA buffer of the M column VGA buffers, and selectively connected to a row-shared row VGA buffer of the N row VGA buffers; and

a per-element selection logic receiving a row selection signal, a column selection signal, and an enable signal to control operation of the transceiver circuit.

14. A method of operating the imaging system of claim 13, the method comprising:

activating the imaging system in column-parallel mode, applying relative delays to selected ones of the column gate drivers to perform azimuth beam-formation, and outputting signals received by selected ones of the column VGA buffers; and

activating the imaging system in row-parallel mode, applying relative delays to selected ones of the row gate drivers to perform elevation beam-formation, and outputting signals received by selected ones of the row VGA buffers.

15. A method of 3D coherent compounding using the imaging system of claim 13, the method comprising:

receiving Rx signal data from the imaging system for a set of transmitted angles along an azimuth direction and along an elevation direction;

generating delay-and-sum beamforming values from the Rx signal data for each of the set of transmitted angles;

generating 3D image values for each of the set of transmitted angles using the delay-and-sum beamforming values; and

performing coherent compounding across the set of transmitted angles by adding voxel values in complex domain.

16. A method of operating the imaging system of claim 13, comprising:

activating interleaved checkerboard patterns of the N×

M array of transducers with I and Q excitations from the column gate drivers or the row gate drivers.

17. A method of operating the imaging system of claim 13, comprising:

activating, according to a programmable pattern, the N×

M array of transducers to form at least one annular ring aperture.

18. A method of electrically removing defective channels in the imaging system of claim 13, the method comprising:

sequentially turning on and off, from each channel of the plurality of transceiver circuits, a transistor of the pulser circuit that selectively connects a ground signal to the transceiver circuit'"'"'s corresponding transducer element; and

storing a per-element enable bit associated with any defective channels determined through leakage current from the sequentially turning on and off of the transistor; and

using the per-element enable bit as the enable signal during operation of the imaging system.

19. A VGA with automatic offset cancelation, the VGA comprising:

at least one differential amplifier; and

a cancelation loop connected at an output of one of the at least one differential amplifier to an input of a second of the at least one differential amplifier.

20. The VGA of claim 19, wherein the at least one differential amplifier comprises three differential amplifiers, the cancelation loop comprising:

a first cancelation loop connected entirely between an output of a first of the three differential amplifiers and an input of a second of the three differential amplifiers that also receives the output of the first of the three differential amplifiers.

21. The VGA of claim 19, wherein the at least one differential amplifier comprises at least two differential amplifiers, the cancelation loop comprising:

a first cancelation loop connected as a feedback loop from an output of one of the at least two differential amplifiers to the input of the second of the at least two differential amplifiers such that the one and the second of the at least two differential amplifiers form part of the feedback loop.

22. The VGA of claim 19, wherein the cancelation loop comprises a feedback loop from an output of an analog-to-digital converter (ADC) to the input of the second of the at least one differential amplifier through a digital-to-analog converter (DAC),

wherein the ADC is connected to the output of the one of the at least one differential amplifier.