Merged TLB Structure For Multiple Sequential Address Translations

• US 20150089116A1
• Filed: 09/26/2013
• Published: 03/26/2015
• Est. Priority Date: 09/26/2013
• Status: Active Grant

• Current Assignee: Marvell Asia Pte Limited (Marvell Technology Group Limited)
• Original Assignee: Cavium, LLC (Marvell Technology Group Limited)
• Inventors: Chin, Bryan W., Mukherjee, Shubhendu S., Snyder, Wilson P. II, Bertone, Michael, Kessler, Richard E.
• Granted Patent: US 9,639,476 B2
• Time in Patent Office: Days
• US Class Current: 711/6
• CPC Class Codes: G06F 12/1027 using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
• CPC Class Codes: G06F 12/1036 for multiple virtual address spaces, e.g. segmentation G06F12/1045 takes precedence
• CPC Class Codes: G06F 2212/151 Emulated environment, e.g. virtual machine

Abstract

A computer system that supports virtualization may maintain multiple address spaces. Each guest operating system employs guest virtual addresses (GVAs), which are translated to guest physical addresses (GPAs). A hypervisor, which manages one or more guest operating systems, translates GPAs to root physical addresses (RPAs). A merged translation lookaside buffer (MTLB) caches translations between the multiple addressing domains, enabling faster address translation and memory access. The MTLB can be logically addressable as multiple different caches, and can be reconfigured to allot different spaces to each logical cache.

Claims

1. A circuit comprising:

a cache configured to store translations between address domains, the cache addressable as a first logical portion and a second logical portion, the first logical portion configured to store translations between a first address domain and a second address domain, the second logical portion configured to store translations between the second address domain and a third address domain;

a processor configured to match an address request against the cache and output a corresponding address result; and

a register configured to define a boundary between the first and second logical portions.

2. The circuit of claim 1, wherein the processor is further configured to match an address request in the first address domain against entries in the first logical portion to determine a corresponding entry having an address in the second address domain.

3. The circuit of claim 2, wherein the processor is further configured to match the entry determined in the first logical portion against entries in the second logical portion to determine a corresponding entry having an address in the third address domain, the address result including the address in the third address domain.

4. The circuit of claim 1, wherein the processor is further configured to match an address request in the second address domain against entries in the second logical portion to determine a corresponding entry having an address in the third address domain, the address result including the address in the third address domain.

5. The circuit of claim 1, wherein at least a subset of entries in the cache includes an index identifier, and further comprising a decoder configured to locate an entry in the cache based on the index identifier.

6. The circuit of claim 5, wherein the address request includes an indication of the index identifier.

7. The circuit of claim 6, wherein the index identifier is configured in a sequence of index identifiers, the order of the sequence being dependent on a source of the address request.

8. The circuit of claim 1, wherein the location of the boundary varies according to a value stored at the register.

9. The circuit of claim 8, wherein a size of at least one of the first and second logical portions varies according to the value stored at the register.

10. The circuit of claim 9, wherein the processor is further configured to update entries in the cache in response to the size of the at least one of the first and second logical portions being varied.

11. The circuit of claim 1, wherein the first address domain is a guest virtual address domain, the second address domain is a guest physical address domain, and the third address domain is a root physical address domain.

12. The circuit of claim 1, wherein each entry in the cache includes a bit indicating whether the entry is a member of the first logical portion or the second logical portion.

13. The circuit of claim 12, wherein the address request includes an indication of the bit corresponding to a requested entry.

14. The circuit of claim 1, wherein the processor is configured to suppress an exception resulting from multiple matching entries during a given time period.

15. The circuit of claim 14, wherein the given time period includes a transition between sources sending the address request.

16. The circuit of claim 1, wherein each entry in the cache includes a bit indicating a source associated with the entry.

17. The circuit of claim 1, wherein the processor is configured to control access to the first portion and the second portion based on a source of the address request.

18. The circuit of claim 1, wherein the a cache is further configured to be addressable as a third logical portion, the third logical portion configured to store translation between the third addressing domain and a fourth addressing domain, and wherein the register is further configured to define a boundary between the second and third logical portions.

19. The circuit of claim 1, wherein the processor is further configured to search a selected one or both of the first and second logical portions based on an indication in the address request.

20. The circuit of claim 1, wherein the processor is further configured, upon detecting a missing entry in the cache for the address request, to output a request for a translation corresponding to the missing entry.

21. The circuit of claim 20, wherein the processor is further configured, upon receiving the translation corresponding to the missing entry, enters the translation into the cache at a randomly-determined entry of a selected on of the first and second logical portions of the cache.

22. The circuit of claim 1, wherein the first logical portion includes a first index and the second logical portion includes a second index, the second index being an inversion of the first index.

23. A method of caching address translations in a memory architecture, comprising:

storing translations between a first address domain and a second address domain to a first logical portion of a cache;

storing translations between the second addressing domain and a third address domain to a second logical portion of the cache;

defining a boundary between the first and second logical portions via a register value; and

matching an address request against the cache and outputting a corresponding address result.

24. The method of claim 23, wherein matching the address request includes matching an address request in the first address domain against entries in the first logical portion to determine a corresponding entry having an address in the second address domain.

25. The method of claim 24, further comprising matching the entry determined in the first logical portion against entries in the second logical portion to determine a corresponding entry having an address in the third address domain, the address result including the address in the third address domain.

26. The method of claim 23, wherein matching the address request includes matching an address request in the second address domain against entries in the second logical portion to determine a corresponding entry having an address in the third address domain, the address result including the address in the third address domain.

27. The method of claim 23, wherein at least a subset of entries in the cache includes an index identifier, and further comprising locating an entry in the cache based on the index identifier.

28. The method of claim 27, wherein the address request includes an indication of the index identifier.

29. The method of claim 28, wherein the index identifier is configured in a sequence of index identifiers, the order of the sequence being dependent on a source of the address request.

30. The method of claim 23, further comprising varying the location of the boundary according to a value stored at the register.

31. The method of claim 30, further comprising varying a size of at least one of the first and second logical portions according to the value stored at the register.

32. The method of claim 31, further comprising updating entries in the cache in response to the size of the at least one of the first and second logical portions being varied.

33. The method of claim 23, wherein the first address domain is a guest virtual address domain, the second address domain is a guest physical address domain, and the third address domain is a root physical address domain.

34. The method of claim 23, wherein each entry in the cache includes a bit indicating whether the entry is a member of the first logical portion or the second logical portion.

35. The method of claim 34, wherein the address request includes an indication of the bit corresponding to a requested entry.

36. The method of claim 23, further comprising suppressing an exception resulting from multiple matching entries during a given time period.

37. The method of claim 36, wherein the given time period includes a transition between sources sending the address request.

38. The method of claim 23, wherein each entry in the cache includes a bit indicating a source associated with the entry.

39. The method of claim 23, further comprising controlling access to the first portion and the second portion based on a source of the address request.

40. The method of claim 23, further comprising:

storing translations between the third addressing domain and a fourth addressing domain; and

defining a boundary between the second and third logical portions.

41. The method of claim 23, further comprising searching a selected one or both of the first and second logical portions based on an indication in the address request.

42. The method of claim 23, further comprising, upon detecting a missing entry in the cache for the address request, outputting a request for a translation corresponding to the missing entry.

43. The method of claim 42, further comprising, upon receiving the translation corresponding to the missing entry, entering the translation into the cache at a randomly-determined entry of a selected one of the first and second logical portions of the cache.

44. The method of claim 23, wherein the first logical portion includes a first index and the second logical portion includes a second index, the second index being an inversion of the first index.

45. A circuit comprising:

a translation lookaside buffer (TLB) configured to store translations between address domains, the TLB addressable as a guest TLB and a root TLB, the guest TLB configured to store translations between a guest virtual address (GVA) domain and a guest physical address (GPA) domain, the root TLB configured to store translations between the GPA domain and a root physical address (RPA) domain, each entry in the cache including a bit indicating whether the entry is a member of the guest TLB or the root TLB;

a processor configured to match an address request against the cache and output a corresponding address result; and

a register configured to define a boundary between the guest TLB and the root TLB.