DISTRIBUTED MEMORY OPERATIONS

• US 20150089162A1
• Filed: 09/26/2013
• Published: 03/26/2015
• Est. Priority Date: 09/26/2013
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Emer, Joel S., Jaleel, Aamer, Parashar, Angshuman, Ahsan, Bushra, Adler, Michael C., Crago, Neal C., Pellauer, Michael I.
• Granted Patent: US 10,331,583 B2
• Time in Patent Office: Days
• US Class Current: 711/147
• CPC Class Codes: G06F 12/0646 Configuration or reconfiguration
• CPC Class Codes: G06F 13/1652 in a multiprocessor architecture interprocessor communication using common memory G06F15/167
• CPC Class Codes: G06F 13/1663 Access to shared memory
• CPC Class Codes: G06F 13/1684 using multiple buses
• CPC Class Codes: G06F 2213/00 Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units

Abstract

A technology for implementing a method for distributed memory operations. A method of the disclosure includes obtaining distributed channel information for an algorithm to be executed by a plurality of spatially distributed processing elements. For each distributed channel in the distributed channel information, the method further associates one or more of the plurality of spatially distributed processing elements with the distributed channel based on the algorithm.

Claims

1. An apparatus comprising:

a memory; and

a processing device communicably coupled to the memory, the processing device to;

obtain distributed channel information for an algorithm to be executed by a plurality of spatially distributed processing elements, wherein the plurality of spatially distributed processing elements connect to a shared memory controller; and

for each distributed channel in the distributed channel information,

associate one or more of the plurality of spatially distributed processing elements with the distributed channel based on the algorithm.

2. The apparatus of claim 1, wherein the processing device is further to:

for each distributed channel in the distributed channel information;

determine whether the distributed channel is associated with a memory operation, and

upon determining the distributed channel is associated with a memory operation, allocate a memory port for the distributed channel to allow the distributed channel to perform the memory operation.

3. The apparatus of claim 2, wherein the memory operation is a load operation, and wherein to associate one or more of the plurality of spatially distributed processing elements with the distributed channel, the processing device is to:

associate a first spatially distributed processing element of the plurality of spatially distributed processing elements with the distributed channel, wherein the first spatially distributed processing element is to generate a load request for the load operation to be sent to the memory using the distributed channel; and

associate a second spatially distributed processing element of the plurality of spatially distributed processing elements with the distributed channel, wherein the second spatially distributed processing element is to obtain load data associated with the load operation from the memory using the distributed channel.

4. The apparatus of claim 2, wherein the memory operation is a store operation, and wherein the processing device is to:

associate a first spatially distributed processing element of the plurality of spatially distributed processing elements with a first distributed channel, wherein the first spatially distributed processing element is to generate a store address for the store operation to be sent to the memory using the first distributed channel; and

associate a second spatially distributed processing element of the plurality of spatially distributed processing elements with a second distributed channel, wherein the second spatially distributed processing element is to generate the store data for the store operation to be sent to the memory using the second distributed channel.

5. The apparatus of claim 1, wherein the processing device is further to:

associate request information with a distributed channel, wherein the request information is used by the memory to determine information about a request from the distributed channel, and wherein the request from the distributed channel does not comprise the information.

6. The apparatus of claim 5, wherein the request information comprises at least one of:

cacheable, not cacheable, coherent, incoherent, end of data, or atomic store.

7. The apparatus of claim 1, wherein the distributed channel information comprises at least one of a first distributed channel associated with store data, a second distributed channel associated with a store address, a third distributed channel associated with a load operation, or a fourth channel associated with an arithmetic operation.

8. The apparatus of claim 1, wherein the processing device is further to:

obtain a memory request to be saved in a completion buffer;

determine if a predetermined number of slots remain in the completion buffer;

upon determining that a predetermined number of slots do not remain in the completion buffer, save the memory request in the completion buffer;

upon determining that a predetermined number of slots remain in the completion buffer;

determine if the memory request is a load request,

upon determining the memory request is a load request, determine whether a source associated with the load request has a destination credit,

upon determining the source associated with the load request has a destination credit, save the memory request in the completion buffer, and

upon determining the source associated with the load request does not have a destination credit, deny the memory request to be saved in the completion buffer until an additional slot is available in the completion buffer.

9. The apparatus of claim 1, wherein the processing device is further to:

obtain a memory request to be saved in a completion buffer;

determine if a predetermined number of slots remain in the completion buffer;

upon determining that a predetermined number of slots do not remain in the completion buffer, save the memory request in the completion buffer;

upon determining that a predetermined number of slots remain in the completion buffer;

determine if the memory request is a store request, and

upon determining the memory request is a store request, deny the memory request to be saved in the completion buffer until an additional slot is available in the completion buffer.

10. The apparatus of claim 1, wherein the processing device is further to:

obtain a first memory request associated with an address;

allocate an entry in an ordering buffer for the first memory request;

determine whether to maintain an order for the first memory request and a second memory request in the ordering buffer; and

upon determining to maintain an order for the first memory request and a second memory request in the ordering buffer, update the ordering buffer to include the order of the first memory request and the second memory request.

11. The apparatus of claim 1, wherein the processing device is further to:

obtain data associated with an address;

determine whether an entry with the address is in an ordering buffer;

upon determining an entry with the address is in the ordering buffer,

service an entry associated with the address, wherein the oldest entry is determined based on an order of memory requests maintained by the ordering buffer,

determine whether an additional entry associated with the address is in the ordering buffer, and

upon determining that an additional entry associated with the address is in the ordering buffer, service the additional entry using the data, wherein the older entry was saved to the ordering buffer before the additional entry was saved to the ordering buffer.

12. A method comprising:

obtaining distributed channel information for an algorithm to be executed by a plurality of spatially distributed processing elements, wherein the plurality of spatially distributed processing elements connect to a shared memory controller; and

for each distributed channel in the distributed channel information,

associating one or more of the plurality of spatially distributed processing elements with the distributed channel based on the algorithm.

13. The method of claim 12, further comprising:

for each distributed channel in the distributed channel information;

determining whether the distributed channel is associated with a memory operation, and

upon determining the distributed channel is associated with a memory operation, allocating a memory port for the distributed channel to allow the distributed channel to perform the memory operation.

14. The method of claim 12, further comprising:

obtaining a memory request to be saved in a completion buffer;

determining if a predetermined number of slots remain in the completion buffer;

upon determining that a predetermined number of slots do not remain in the completion buffer, saving the memory request in the completion buffer;

upon determining that a predetermined number of slots remain in the completion buffer;

determining if the memory request is a load request,

upon determining the memory request is a load request, determining whether a source associated with the load request has a destination credit,

upon determining the source associated with the load request has a destination credit, saving the memory request in the completion buffer, and

upon determining the source associated with the load request does not have a destination credit, denying the memory request to be saved in the completion buffer until an additional slot is available in the completion buffer.

15. The method of claim 12, further comprising:

obtaining a memory request to be saved in a completion buffer;

determining if a predetermined number of slots remain in the completion buffer;

upon determining that a predetermined number of slots do not remain in the completion buffer, saving the memory request in the completion buffer;

upon determining that a predetermined number of slots remain in the completion buffer;

determining if the memory request is a store request, and

upon determining the memory request is a store request, denying the memory request to be saved in the completion buffer until an additional slot is available in the completion buffer.

16. The method of claim 12, further comprising:

obtaining a first memory request associated with an address;

allocating an entry in an ordering buffer for the first memory request;

determining whether to maintain an order for the first memory request and a second memory request in the ordering buffer; and

upon determining to maintain an order for the first memory request and a second memory request in the ordering buffer, updating the ordering buffer to include the order of the first memory request and the second memory request.

17. The method of claim 12, further comprising:

obtaining data associated with an address;

determining whether an entry with the address is in an ordering buffer;

upon determining an entry with the address is in the ordering buffer,

servicing an entry associated with the address, wherein the oldest entry is determined based on an order of memory requests maintained by the ordering buffer,

determining whether an additional entry associated with the address is in the ordering buffer, and

upon determining that an additional entry associated with the address is in the ordering buffer, servicing the additional entry using the data, wherein the older entry was saved to the ordering buffer before the additional entry was saved to the ordering buffer.

18. A non-transitory machine-readable storage medium including instructions that, when executed by a processing device, cause the processing device to perform operations comprising:

obtaining distributed channel information for an algorithm to be executed by a plurality of spatially distributed processing elements, wherein the plurality of spatially distributed processing elements connect to a shared memory controller; and

for each distributed channel in the distributed channel information,

associating one or more of the plurality of spatially distributed processing elements with the distributed channel based on the algorithm.

19. The non-transitory machine-readable storage medium of claim 18, wherein the operations further comprise:

for each distributed channel in the distributed channel information;

determining whether the distributed channel is associated with a memory operation, and

upon determining the distributed channel is associated with a memory operation, allocating a memory port for the distributed channel to allow the distributed channel to perform the memory operation.

20. The non-transitory machine-readable storage medium of claim 18, wherein the operations further comprise:

obtaining a memory request to be saved in a completion buffer;

determining if a predetermined number of slots remain in the completion buffer;

upon determining that a predetermined number of slots do not remain in the completion buffer, saving the memory request in the completion buffer;

upon determining that a predetermined number of slots remain in the completion buffer;

determining if the memory request is a load request,

upon determining the memory request is a load request, determining whether a source associated with the load request has a destination credit,

upon determining the source associated with the load request has a destination credit, saving the memory request in the completion buffer, and

upon determining the source associated with the load request does not have a destination credit, denying the memory request to be saved in the completion buffer until an additional slot is available in the completion buffer.

21. The non-transitory machine-readable storage medium of claim 18, wherein the operations further comprise:

obtaining a memory request to be saved in a completion buffer;

determining if a predetermined number of slots remain in the completion buffer;

upon determining that a predetermined number of slots do not remain in the completion buffer, saving the memory request in the completion buffer;

upon determining that a predetermined number of slots remain in the completion buffer;

determining if the memory request is a store request, and

upon determining the memory request is a store request, denying the memory request to be saved in the completion buffer until an additional slot is available in the completion buffer.

22. The non-transitory machine-readable storage medium of claim 18, wherein the operations further comprise:

obtaining a first memory request associated with an address;

allocating an entry in an ordering buffer for the first memory request;

determining whether to maintain an order for the first memory request and a second memory request in the ordering buffer; and

upon determining to maintain an order for the first memory request and a second memory request in the ordering buffer, updating the ordering buffer to include the order of the first memory request and the second memory request.

23. The non-transitory machine-readable storage medium of claim 18, wherein the operations further comprise:

obtaining data associated with an address;

determining whether an entry with the address is in an ordering buffer;

upon determining an entry with the address is in the ordering buffer,

servicing an entry associated with the address, wherein the oldest entry is determined based on an order of memory requests maintained by the ordering buffer,

determining whether an additional entry associated with the address is in the ordering buffer, and

upon determining that an additional entry associated with the address is in the ordering buffer, servicing the additional entry using the data, wherein the older entry was saved to the ordering buffer before the additional entry was saved to the ordering buffer.