NESTED CHANNEL ADDRESS INTERLEAVING

• US 20150089168A1
• Filed: 09/20/2013
• Published: 03/26/2015
• Est. Priority Date: 09/20/2013
• Status: Active Grant

• Current Assignee: Advanced Micro Devices, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Kalyanasundharam, Vydhyanathan, Brandl, Kevin M., Dhanani, Adnan
• Granted Patent: US 9,141,541 B2
• Time in Patent Office: Days
• US Class Current: 711/157
• CPC Class Codes: G06F 12/0607 Interleaved addressing

Abstract

A system and method for mapping an address space to a non-power-of-two number of memory channels. Addresses are translated and interleaved to the memory channels such that each memory channel has an equal amount of mapped address space. The address space is partitioned into two regions, and a first translation function is used for memory requests targeting the first region and a second translation function is used for memory requests targeting the second region. The first translation function is based on a first set of address bits and the second translation function is based on a second set of address bits.

Claims

1. A method comprising:

partitioning an address space into at least a first portion and a second portion;

translating first memory requests targeted to the first portion using a first set of memory request address bits such that the first memory requests are interleaved across N separate memory channels; and

translating second memory requests targeted to the second portion using a second set of memory request address bits different from said first set of memory request address bits;

wherein each memory channel is mapped to an equal amount of the address space.

2. The method as recited in claim 1, wherein the first and second portions of the address space comprise the entirety of the address space, and wherein the N memory channels are equal-sized.

3. The method as recited in claim 1, further comprising adding a first number of bits to the translated and interleaved address of a given memory request when sending the given memory request to a corresponding memory channel.

4. The method as recited in claim 1, wherein the first set of memory request address bits includes a first number of bits, wherein the second set of memory request address bits includes a second number of bits, and wherein the first number is different than the second number.

5. The method as recited in claim 1, wherein N is equal to three.

6. The method as recited in claim 1, wherein N is a non-power-of-two positive integer, and wherein the second memory requests are interleaved across N separate memory channels.

7. The method as recited in claim 1, wherein the first portion of the address space is mapped unevenly to the N memory channels.

8. A computing system comprising:

N memory channels; and

circuitry configured to;

partition an address space into at least a first region and a second region;

apply a first translation function to memory requests targeted to the first region, wherein the first translation function interleaves addresses across the N memory channels; and

apply a second translation function to memory requests targeted to the second region, wherein the second translation function interleaves addresses across the N memory channels, wherein the first and second translation functions evenly map the address space to the N memory channels, and wherein the second translation function is different than the first translation function.

9. The computing system as recited in claim 8, wherein N is equal to three.

10. The computing system as recited in claim 9, wherein the first region is two thirds of the address space, and wherein the second region is one third of the address space.

11. The computing system as recited in claim 10, wherein the first translation function is based on three address bits of a memory request, and wherein the second translation function is based on four address bits of a memory request.

12. The computing system as recited in claim 8, wherein N is a non-power-of-two positive integer.

13. The computing system as recited in claim 8, wherein the N memory channels are equal-sized.

14. The computing system as recited in claim 8, wherein the first region of the address space is mapped unevenly to the N memory channels.

15. A non-transitory computer readable storage medium storing program instructions, wherein the program instructions are executable to:

partition an address space into at least a first portion and a second portion;

translate first memory requests targeted to the first portion using a first set of memory request address bits such that the first memory requests are interleaved across N separate memory channels; and

translate second memory requests targeted to the second portion using a second set of memory request address bits different from the first set of memory request address bits such that the second memory requests are interleaved across N separate memory channels;

wherein each memory channel is mapped to an equal amount of the address space.

16. The non-transitory computer readable storage medium as recited in claim 15, wherein N is equal to three.

17. The non-transitory computing system as recited in claim 16, wherein the first region is two thirds of the address space, and wherein the second region is one third of the address space.

18. The non-transitory computing system as recited in claim 17, wherein the first translation function is based on three address bits of a memory request, and wherein the second translation function is based on four address bits of the memory request.

19. The non-transitory computing system as recited in claim 15, wherein N is a non-power-of-two positive integer.

20. The non-transitory computing system as recited in claim 16, wherein the three memory channels are equal-sized.