PREDICTIVE FETCHING AND DECODING FOR SELECTED INSTRUCTIONS

• US 20150089194A1
• Filed: 12/03/2014
• Published: 03/26/2015
• Est. Priority Date: 06/28/2013
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Gschwind, Michael K., Salapura, Valentina
• Granted Patent: US 9,619,232 B2
• Time in Patent Office: Days
• US Class Current: 712/205
• CPC Class Codes: G06F 9/30054 Unconditional branch instructions
• CPC Class Codes: G06F 9/30058 Conditional branch instructions
• CPC Class Codes: G06F 9/30145 Instruction analysis, e.g. decoding, instruction word fields
• CPC Class Codes: G06F 9/3016 Decoding the operand specifier, e.g. specifier format
• CPC Class Codes: G06F 9/323 for indirect branch instructions
• CPC Class Codes: G06F 9/3802 Instruction prefetching
• CPC Class Codes: G06F 9/3806 using address prediction, e.g. return stack, branch history buffer
• CPC Class Codes: G06F 9/382 Pipelined decoding, e.g. using predecoding
• CPC Class Codes: G06F 9/3836 Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
• CPC Class Codes: G06F 9/384 Register renaming
• CPC Class Codes: G06F 9/3842 Speculative instruction execution
• CPC Class Codes: G06F 9/3854 Instruction completion, e.g. retiring, committing or graduating
• CPC Class Codes: G06F 9/3858 Result writeback, i.e. updating the architectural state or memory
• CPC Class Codes: G06F 9/3861 Recovery, e.g. branch miss-prediction, exception handling error detection or correction G06F11/00
• CPC Class Codes: G06F 9/3867 using instruction pipelines

Abstract

Predictive fetching and decoding for selected instructions (e.g., operating system instructions, hypervisor instructions or other such instructions). A determination is made that a selected instruction, such as a system call instruction, an asynchronous interrupt, a return from system call instruction or return from asynchronous interrupt, is to be executed. Based on determining that such an instruction is to be executed, a predicted address is determined for the selected instruction, which is the address to which processing transfers in order to provide the requested services. Then, fetching of instructions beginning at the predicted address prior to execution of the selected instruction is commenced. Further, speculative state relating to a selected instruction, including, for instance, an indication of the privilege level of the selected instruction or instructions executed on behalf of the selected instruction, is predicted and maintained.

Claims

1. A method of facilitating processing within a processing environment, the method comprising:

predicting that a selected instruction is to execute in a pipelined processor, the pipelined processor having a plurality of stages of processing including an execute stage, and the selected instruction having a first privilege level and one or more other instructions executing in the pipelined processor having a second privilege level different from the first privilege level;

based on predicting the selected instruction is to execute, predicting an entry address for the selected instruction and operating state associated therewith, the entry address indicating a location at which an instruction is to be fetched based on the selected instruction;

based on predicting the entry address, fetching the instruction at the entry address prior to the selected instruction reaching the execute stage; and

initiating decoding of the fetched instruction based on the predicted operating state.

2. The method of claim 1, further comprising executing the selected instruction, wherein the executing comprises:

updating a non-speculative operating state of the selected instruction based on executing the selected instruction;

comparing the non-speculative operating state with the predicted operating state; and

based on the comparing indicating a discrepancy, performing recovery.

3. The method of claim 2, wherein the performing recovery comprises:

performing a flush of the pipelined processor, the performing the flush providing a new fetch address and new speculative operating state;

based on performing the flush, initiating a fetch of an instruction at the new fetch address; and

processing the instruction fetched at the new fetch address based on the new speculative operating state.

4. The method of claim 1, further comprising placing a return address for the selected instruction in an entry within a data structure, the return address to indicate an address to which processing is to return.

5. The method of claim 4, further comprising including within the entry at least one of operating state for the return address and an indicator of a creator of the entry.

6. The method of claim 1, wherein the operating state comprises a predicted privilege level for the instruction at the entry address, and wherein the method further comprises storing the predicted operating state in a data structure coupled to a decode unit of the processing environment, the decode unit to decode the fetched instruction based on the predicted operating state.

7. The method of claim 1, wherein the predicting the entry address comprises predicting the entry address based on one of a fixed value, a value in a register, or a cached value.

8. The method of claim 1, wherein the predicting comprises using branch prediction logic to predict that the selected instruction is to execute.

9. The method of claim 1, wherein the predicting the operating state comprises predicting a privilege level for the instruction at the entry address, the predicting the privilege level comprising predicting the privilege level based on one or more parameters associated with the selected instruction.

10. The method of claim 1, wherein the selected instruction comprises one of a system call instruction, a hypervisor call instruction or an asynchronous interrupt.