ENTROPY STORAGE RING HAVING STAGES WITH FEEDBACK INPUTS

• US 20150089242A1
• Filed: 09/25/2013
• Published: 03/26/2015
• Est. Priority Date: 09/25/2013
• Status: Active Grant

• Current Assignee: Netronome Systems Incorporated
• Original Assignee: Netronome Systems Incorporated
• Inventors: Stark, Gavin J.
• Granted Patent: US 9,092,284 B2
• Time in Patent Office: Days
• US Class Current: 713/189
• CPC Class Codes: G06F 7/58 Random or pseudo-random number generators

Abstract

An entropy storage ring includes an input node, a plurality of serial-connected stages, and an output node. Each stage includes an XOR (or XNOR) circuit, a delay element having an input coupled to the XOR output, and a combinatorial circuit having an output coupled to a second input of the XOR. The combinatorial circuit may be a NAND, NOR, AND or OR gate. A first input of the XOR is the data input of the stage. The output of the delay element is the data output of the stage. A first input of the combinatorial circuit is coupled to receive an enable bit from a configuration register. A second input of the combinatorial circuit is coupled to the ring output node. In operation, a bit stream is supplied onto the ring input node. Feedback of multiple stages are enabled so that the bit stream undergoes complex permutation as it circulates.

Claims

1. A circuit comprising:

a configuration register that outputs a plurality of enable bit signals; and

signal storage ring comprising;

a signal storage ring input node;

a signal storage ring output node; and

a plurality of stages, wherein each of at least two of the stages comprises;

an exclusive OR circuit having a first input lead, a second input lead, and an output lead, wherein the first input lead of the exclusive OR circuit is a ring data input of the stage;

a combinatorial logic circuit having a first input lead, a second input lead, and an output lead, wherein the output lead of the combinatorial logic circuit is coupled to the second input lead of the exclusive OR circuit, wherein the second input lead of the combinatorial logic circuit is coupled to the signal storage ring output node, wherein the input lead of the combinatorial logic circuit is coupled to receive one of the enable bit signals; and

a delay element having an input lead and an output lead, wherein the input lead of the delay element is coupled the output lead of the exclusive OR circuit, wherein the output lead of the delay element is a ring data output of the stage, and wherein the delay element is taken from the group consisting of;

a single inverter, an odd number of series-connected inverters, an even number of series-connected inverters.

2. The circuit of claim 1, wherein a non-inverting signal path extends from the signal storage ring input node, through the plurality of stages, and to the signal storage ring output node.

3. The circuit of claim 1, wherein an inverting signal path extends from the signal storage ring input node, through the plurality of stages, and to the signal storage ring output node.

4. The circuit of claim 1, wherein each of the enable bit signals output by the configuration register is supplied onto the first input lead of the combinatorial logic circuit of a corresponding one of the plurality of stages.

5. The circuit of claim 1, wherein the combinatorial logic circuit is taken from the group consisting of:

a two-input NAND circuit, a two-input AND circuit, a two-input NOR circuit, a two-input OR circuit.

6. The circuit of claim 1, wherein each of the stages is logically identical to each of the other stages.

7. The circuit of claim 1, wherein at least one of the stages is not logically identical to another of the stages.

8. The circuit of claim 1, wherein the signal storage ring input node is an input of a first of the plurality of stages, and wherein the signal storage ring output node is an output of a second of the plurality of stages.

9. The circuit of claim 1, wherein the signal storage ring is configurable to operate as a ring oscillator.

10. The circuit of claim 1, further comprising:

a multiplexer, wherein a first data input of the multiplexer is coupled to the signal storage ring input node, and wherein a second data input of the multiplexer is coupled to the signal storage ring output node.

11. The circuit of claim 1, wherein the signal storage ring input node is coupled to receive a bit stream from a self-timed logic circuit.