SYSTEM POWER MANAGEMENT USING COMMUNICATION BUS PROTOCOLS

• US 20150089259A1
• Filed: 09/20/2013
• Published: 03/26/2015
• Est. Priority Date: 09/20/2013
• Status: Active Grant

• Current Assignee: Apple Inc.
• Original Assignee: Apple Inc.
• Inventors: Warren, David S., Levit, Inna, Paaske, Timothy R.
• Granted Patent: US 9,395,795 B2
• Time in Patent Office: Days
• US Class Current: 713/322
• CPC Class Codes: G06F 1/06 Clock generators producing several clock signals G06F1/08 - G06F1/14 take precedence
• CPC Class Codes: G06F 1/08 Clock generators with changeable or programmable clock frequency
• CPC Class Codes: G06F 1/3206 Monitoring of events, devices or parameters that trigger a change in power modality
• CPC Class Codes: G06F 1/3237 by disabling clock generation or distribution
• CPC Class Codes: G06F 1/325 Power saving in peripheral device
• CPC Class Codes: G06F 1/3296 by lowering the supply or operating voltage
• CPC Class Codes: G06F 13/4022 using switching circuits, e.g. switching matrix, connection or expansion network G06F13/4009 takes precedence
• CPC Class Codes: G06F 13/4282 on a serial bus, e.g. I2C bus, SPI bus on daisy chain buses G06F13/4247
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management
• CPC Class Codes: Y02D 30/50 in wire-line communication networks, e.g. low power modes or reduced link rate

Abstract

Embodiments of an apparatus and method are disclosed that may allow for managing power of a computing system. The apparatus may include a clock generation circuit, a bus interface unit, and a control circuit. The clock generation circuit may be configured to generate multiple clock signals. Each clock signal may provide a timing reference to different functional blocks within a device coupled to the communication bus. The bus interface unit may be configured to receive messages from the device via the communication bus. The messages may include a latency value and a request to activate a low power mode. The control circuit may be configured to deactivate one or more of the multiple clock signals dependent upon the latency value and multiple threshold values.

Claims

1. An apparatus, comprising:

a clock generation circuit configured to generate a first clock signal and a second clock signal, wherein the first clock signal provides a timing reference to an interface unit of a device, and the second clock signal provides a timing reference to one or more logic blocks of the device;

a bus interface unit coupled to a communication bus, wherein the bus interface unit is configured to;

receive a message from a device, wherein the message includes a latency value, and

receive a request signal from the device, wherein the request signal indicates a request from the second device to activate a low power mode;

a control circuit configured to;

send an acknowledged signal to the device responsive to receiving the second message, wherein the acknowledged signal indicates that the low power mode of the device may be activated;

deactivate the first clock signal responsive to a determination that the latency value is greater than a first threshold value and less than a second threshold value; and

deactivate the first clock signal and the second clock signal responsive to a determination that the latency value is greater than the second threshold value.

2. The apparatus of claim 1, wherein the latency value includes a latency number and a scale factor.

3. The apparatus of claim 2, wherein to deactivate the first clock signal the control circuit is further configured to multiply the latency value by the scale factor.

4. The apparatus of claim 1, wherein the control circuit is further configured to send an acknowledged signal to the device responsive to receiving the request signal, wherein the acknowledged signal indicates that the low power mode of the device may be activated.

5. The apparatus of claim 4, wherein to receive the request signal, the bus interface unit is further configured to receive a request message via the communication bus.

6. The apparatus of claim 1, wherein the clock generation circuit includes a phase-locked loop (PLL).

7. A method for operating a computing system, comprising:

sending a first message from a first component of the computing system to a second component of the computing system, wherein the first message includes a latency value;

sending a request signal from the first component of the computing system to the second component of the computing system, wherein the request signal includes a request for the first component to activate a low power mode;

activating a first low power mode for the first component responsive a determination that the latency value is greater than a first threshold value and less than a second threshold value; and

activating a second low power mode for the first component responsive to a determination that the latency value is greater than the second threshold value.

8. The method of claim 7, wherein activating the first low power mode comprises deactivating a first clock signal, wherein the first clock signal provides a timing reference to an interface unit of the first component of the computing system.

9. The method of claim 8, wherein activating the second low power mode comprises deactivating the first clock signal and a second clock signal, wherein the second clock signal provides a timing reference to one or more logic blocks of the first component of the computing system, and wherein the one or more logic blocks excludes the interface unit.

10. The method of claim 7, wherein the sent latency value includes a latency number and a scale factor.

11. The method of claim 9, wherein activating the first low power mode comprises multiplying the latency number by the scale factor.

12. The method of claim 8, wherein activating the second low power mode comprises reducing a voltage level of a power supply to one or more logic blocks of the first component of the computing system.

13. The method of claim 12, wherein activating the second low power mode further comprises deactivating a first clock signal, wherein the first clock signal provides a timing reference to an interface unit of the first component of the computing system.

14. The method of claim 13, wherein activating the second low power mode further comprises deactivating the first clock signal and a second clock signal, wherein the second clock signal provides a timing reference to the one or more logic blocks of the first component of the computing system, and wherein the one or more logic blocks excludes the interface unit.

15. A system, comprising:

a host configured to generate a first clock signal and a second clock signal; and

a device coupled to the host via a communication bus, wherein the device is configured to;

receive the first clock signal and the second clock signal; and

wherein the first clock signal provides a timing reference to an interface unit of the device, and the second clock signal provides a timing reference to one or more logic blocks of the device, wherein the one or more logic blocks excludes the interface unit;

send a first message to the host, wherein the first message includes a latency value; and

send a request signal to the host, wherein the request signal includes a request for the device to activate a low power mode;

wherein the host is further configured to;

deactivate the first clock signal responsive to receiving the request signal and a determination that the latency value is greater than a first threshold value and less than a second threshold value; and

deactivate the first clock signal and the second clock signal responsive to receiving the request signal and a determination that the latency value is greater than the second threshold value.

16. The system of claim 15, the host is further configured to acknowledge the request send by the device to activate the low power mode.

17. The system of claim 16, to send the request signal, the device is further configured to send a request message via the communication bus.

18. The system of claim 15, wherein the latency value includes a latency number and a scale factor.

19. The system of claim 18, wherein to deactivate the first clock signal, the host is further configured to multiply the latency number by the scale factor.

20. The system of claim 15, wherein the device comprises a phase-locked loop (PLL), wherein the PLL is configured to receive the second clock signal.