RRAM CELL STRUCTURE WITH LATERALLY OFFSET BEVA/TEVA

• US 20150090949A1
• Filed: 09/30/2013
• Published: 04/02/2015
• Est. Priority Date: 09/30/2013
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Chang, Chih-Yang, Chu, Wen-Ting, Tu, Kuo-Chi, Liao, Yu-Wen, Yang, Chin-Chieh, Chen, Hsai-Wei, Shih, Sheng-Hung, You, Wen-Chun
• Granted Patent: US 9,112,148 B2
• Time in Patent Office: Days
• US Class Current: 257/4
• CPC Class Codes: H10B 63/30 comprising selection components having three or more electrodes, e.g. transistors
• CPC Class Codes: H10N 70/011 Manufacture or treatment of multistable switching devices
• CPC Class Codes: H10N 70/021 Formation of switching materials, e.g. deposition of layers
• CPC Class Codes: H10N 70/023 by chemical vapor deposition, e.g. MOCVD, ALD
• CPC Class Codes: H10N 70/026 by physical vapor deposition, e.g. sputtering
• CPC Class Codes: H10N 70/028 by conversion of electrode material, e.g. oxidation
• CPC Class Codes: H10N 70/041 Modification of switching materials after formation, e.g. doping shaping H10N70/061
• CPC Class Codes: H10N 70/043 by implantation
• CPC Class Codes: H10N 70/046 by diffusion, e.g. photo-dissolution
• CPC Class Codes: H10N 70/061 Shaping switching materials
• CPC Class Codes: H10N 70/063 by etching of pre-deposited switching material layers, e.g. lithography
• CPC Class Codes: H10N 70/066 by filling of openings, e.g. damascene method
• CPC Class Codes: H10N 70/068 by processes specially adapted for achieving sub-lithographic dimensions, e.g. using spacers
• CPC Class Codes: H10N 70/20 Multistable switching devices, e.g. memristors
• CPC Class Codes: H10N 70/231 based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect
• CPC Class Codes: H10N 70/235 between different crystalline phases, e.g. cubic and hexagonal
• CPC Class Codes: H10N 70/24 based on migration or redistribution of ionic species, e.g. anions, vacancies
• CPC Class Codes: H10N 70/245 the species being metal cations, e.g. programmable metallization cells
• CPC Class Codes: H10N 70/25 based on bulk electronic defects, e.g. trapping of electrons
• CPC Class Codes: H10N 70/253 having three or more electrodes, e.g. transistor-like devices
• CPC Class Codes: H10N 70/257 : having switching assisted by radiation or particle beam, e.g. optically controlled devices
• CPC Class Codes: H10N 70/801 : Constructional details of multistable switching devices
• CPC Class Codes: H10N 70/821 : Device geometry
• CPC Class Codes: H10N 70/823 : adapted for essentially horizontal current flow, e.g. bridge type devices
• CPC Class Codes: H10N 70/826 : adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
• CPC Class Codes: H10N 70/8265 : on sidewalls of dielectric structures, e.g. mesa-shaped or cup-shaped devices
• CPC Class Codes: H10N 70/828 : Current flow limiting means within the switching material region, e.g. constrictions
• CPC Class Codes: H10N 70/841 : Electrodes
• CPC Class Codes: H10N 70/8413 : adapted for resistive heating
• CPC Class Codes: H10N 70/8416 : adapted for supplying ionic species
• CPC Class Codes: H10N 70/8418 : adapted for focusing electric field or current, e.g. tip-shaped
• CPC Class Codes: H10N 70/8613 : Heating or cooling means other than resistive heating electrodes, e.g. heater in parallel
• CPC Class Codes: H10N 70/8616 : Thermal insulation means
• CPC Class Codes: H10N 70/881 : Switching materials
• CPC Class Codes: H10N 70/882 : Compounds of sulfur, selenium or tellurium, e.g. chalcogenides
• CPC Class Codes: H10N 70/8822 : Sulfides, e.g. CuS
• CPC Class Codes: H10N 70/8825 : Selenides, e.g. GeSe
• CPC Class Codes: H10N 70/8828 : Tellurides, e.g. GeSbTe
• CPC Class Codes: H10N 70/883 : Oxides or nitrides
• CPC Class Codes: H10N 70/8833 : Binary metal oxides, e.g. TaOx
• CPC Class Codes: H10N 70/8836 : Complex metal oxides, e.g. perovskites, spinels
• CPC Class Codes: H10N 70/884 : based on at least one element of group IIIA, IVA or VA, e.g. elemental or compound semiconductors compounds of sulfur, selenium or tellurium, e.g. chalcogenides H10N70/882; oxides or nitrides H10N70/883
• CPC Class Codes: H10N 70/8845 : Carbon or carbides

Abstract

The present disclosure relates to a resistive random access memory (RRAM) cell architecture, with off-axis or laterally offset top electrode via (TEVA) and bottom electrode via (BEVA). Traditional RRAM cells having a TEVA and BEVA that are on-axis can cause high contact resistance variations. The off-axis TEVA and BEVA in the current disclosure pushes the TEVA away from the insulating layer over the RRAM cell, which can improve the contact resistance variations. The present disclosure also relates to a memory device having a rectangular shaped RRAM cell having a larger area that can lower the forming voltage and improve data retention.

Claims

1. A resistive random access memory (RRAM) device comprising:

a resistive random-access memory (RRAM) cell having a first surface and a second surface;

a first conductive interconnect structure abutting the first surface at a first location; and

a second conductive interconnect structure abutting the second surface at a second location, wherein the first and second locations are laterally offset from one another.

2. The RRAM device of claim 1, wherein the RRAM cell comprises:

a variable resistive dielectric layer having a top surface and a bottom surface;

a top electrode disposed over the variable resistive dielectric layer abutting the top surface;

a bottom electrode disposed below the variable resistive dielectric layer abutting the bottom surface;

a top electrode via (TEVA) that abuts the top electrode; and

a bottom electrode via (BEVA) that abuts the bottom electrode.

3. The RRAM device of claim 2, wherein the TEVA corresponds to the first conductive interconnect structure and is positioned at the first location, and wherein the BEVA corresponds to the second conductive interconnect structure and is positioned at the second location which is laterally offset from the first location.

4. The RRAM device of claim 2 further comprising:

a semiconductor area comprising a metal disposed within an extremely low-k dielectric layer formed thereover;

a dielectric protection layer having an open region above the metal, wherein sidewalls of dielectric protection layer end with rounded ends above the metal;

an insulating layer abutting the top electrode above the open region; and

,

spacers located on opposing sides of the top electrode.

5. The RRAM device of claim 4, wherein:

the bottom electrode via (BEVA) resides over a defined region above the dielectric protection layer, follows a shape of the rounded ends of the dielectric protection layer in a dipping fashion and resides over the open region contacting the metal in the semiconductor area;

the bottom electrode is disposed entirely over the BEVA;

the variable resistive dielectric layer is disposed entirely over the BE;

the top electrode resides over a defined region above the variable resistive dielectric layer; and

the TEVA resides at a location that is laterally offset from the open region and the insulating layer.

6. The RRAM device of claim 1, wherein the RRAM cell comprises a length dimension and a breadth dimension constituting an area, and wherein the first conductive interconnect structure and the second conductive interconnect structure are disposed within the area.

7. The RRAM device of claim 1, where in a shape of the RRAM cell is rectangular.

8. The RRAM device of claim 5, wherein the top electrode comprises Tantalum Nitride (TaN) over Titanium (Ti), the bottom electrode comprises titanium nitride (TiN), the TEVA comprises copper (Cu), the BEVA comprises TaN, the variable resistive dielectric layer comprises Hafnium oxide (HfO), the spacer comprises silicon nitride (SiN) and the insulating layer comprises silicon ox nitride (SiON).

9. A resistive random access memory (RRAM) device, comprising:

a semiconductor body having a source region and a drain region horizontally separated by a channel region;

a gate structure disposed over the channel region;

a first contact and a second contact extending upwardly from the drain and source regions, respectively;

a first conductive interconnect structure formed over the first contact and electrically coupled to the first contact;

a RRAM cell formed over the first conductive interconnect and having a first surface and a second surface, wherein the first surface is coupled to the first conductive interconnect at a first location; and

a second conductive interconnect structure formed over the RRAM cell and abutting the second surface at a second location, wherein the first and second locations are laterally offset with respect to one another.

10. The memory device of claim 9, wherein the gate structure is coupled to a word line.

11. The memory device of claim 9, wherein the gate structure comprises a poly-silicon gate electrode formed over a gate dielectric which electrically isolates the gate electrode from the channel region.

12. The memory device of claim 9, wherein one or more metal contacts and one or more metal contact vias exist between the source region and the second contact and between the drain region and the first contact.

13. The memory device of claim 9, wherein the source region is coupled to a source line and the drain region is coupled to a bit line.

14. The memory device of claim 9, wherein the source and drain regions have a first conductivity and the semiconductor body has a second conductivity.

15-20. -20. (canceled)

21. A resistive random access memory (RRAM) cell of a memory device, comprising:

a variable resistive dielectric layer having a top surface and a bottom surface;

a top electrode (TE) disposed over the top surface of the variable resistive dielectric layer;

a bottom electrode (BE) disposed below the bottom surface of the variable resistive dielectric layer;

a top electrode via (TEVA) that abuts the top electrode, wherein the TEVA is centered at a first location; and

a bottom electrode via (BEVA) that abuts the bottom electrode wherein the BEVA is centered at a second location which is laterally offset from the first location.

22. The memory device of claim 21, further comprising:

a semiconductor area comprising a metal disposed within an extreme low-k dielectric layer formed thereover;

a dielectric protection layer having an open region above the metal, wherein sidewalls of dielectric protection layer end with rounded ends above the metal;

an insulating layer abutting the top electrode above the open region; and

spacers located on opposing sides of the top electrode.

23. The memory device of claim 22, wherein:

the bottom electrode via (BEVA) resides over a defined region above the dielectric protection layer, follows a shape of the rounded ends of the dielectric protection layer in a dipping fashion and resides over the open region contacting the metal in the semiconductor area;

the bottom electrode is disposed entirely over the BEVA;

the variable resistive dielectric layer is disposed entirely over the BE; and

the top electrode resides over a defined region above the variable resistive dielectric layer.

24. The memory device of claim 22, wherein the first location of the TEVA is laterally offset from the open region and the insulating layer.

25. The memory device of claim 21, wherein the RRAM cell comprises a length dimension and a breadth dimension constituting an area, and wherein the TEVA and the BEVA are disposed within the area.

26. The memory device of claim 21, further comprising:

a semiconductor body having a source region and a drain region horizontally separated by a channel region;

a gate structure disposed over the channel region and connected to a word line;

a first overlying contact coupled to the source region and connected to a source line; and

a second overlying contact disposed above the TEVA, coupled to the drain region through the RRAM cell, and connected to a bit line.