POWER MOSFET DEVICES INCLUDING EMBEDDED SCHOTTKY DIODES AND METHODS OF FABRICATING THE SAME

• US 20150091084A1
• Filed: 07/03/2014
• Published: 04/02/2015
• Est. Priority Date: 09/27/2013
• Status: Abandoned Application

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: In-Ho Yeo, Jung-Ho Lee
• Inventors: Oh, Sae-Choon, Lee, Suk-Kyun, Lee, Heon-Bok, Yeo, In-ho, Lee, Jung-ho
• Application Number:
  US14/323,731
• Publication Number:
  US 20150091084A1
• Time in Patent Office: Days
• US Class Current: 257/334
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 29/0869 Shape cell layout H01L29/0696
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/66143 Schottky diodes
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7806 the other device being a Schottky barrier diode
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/872 Schottky diodes

Abstract

A semiconductor device can include first and second vertical channel power MOSFET transistors that are arranged in a split-gate configuration in a semiconductor substrate. A groove can be in an active region between the first and second vertical channel power MOSFET transistors and a conductive pattern can be in the groove on the active region, where the conductive pattern can include a source contact for the first and second vertical channel power MOSFET transistors. A vertical Schottky semiconductor region can be embedded in the groove beneath the conductive pattern between the vertical channels.

Claims

1. A semiconductor device, comprising:

a semiconductor substrate;

an epi-semiconductor layer disposed on the semiconductor substrate;

trenches disposed in the epi-semiconductor layer defining an active region between the trenches;

a groove region disposed in an upper surface of the active region and separating first and second active protrusions of the active region;

a gate structure disposed in each of the trenches;

a front-side conductive pattern in the groove region;

a first conductivity-type drift region, first and second body channel regions, and first and second source regions configured to form a transistor with the gate structure, wherein the first conductivity-type drift region is disposed in the active region of the epi-semiconductor layer, wherein the first and second body channel regions have a second conductivity-type different from the first conductivity-type and are spaced apart from each other, and wherein the first and second source regions have the first conductivity-type and are spaced apart from each other on opposite sides of the groove region; and

a Schottky semiconductor region having the first conductivity-type disposed between the first and second body channel regions in the groove region and in the active region under a bottom surface of the groove region, and configuring a Schottky diode with the front-side conductive pattern.

2. The semiconductor device of claim 1, wherein the Schottky semiconductor region includes 13th and 15th group elements of the long-form Periodic Table, and an amount per unit volume of the 15th group element is greater than that of the 13th group element in the Schottky semiconductor region, and

wherein the drift region adjacent to the Schottky semiconductor region includes the amount per unit volume of the 15th group element that is in the Schottky semiconductor region, and the drift region includes a higher majority carrier concentration than in the Schottky semiconductor region.

3. The semiconductor device of claim 1, wherein the first source region is disposed in the first active protrusion, and the second source region is disposed in the second active protrusion, and

wherein bottoms of the first and second source regions are located at a higher level nearer to the groove region than nearer to the trenches.

4. The semiconductor device of claim 1, wherein the first and second body channel regions are disposed on the drift region,

the first source region is disposed on the first body channel region,

the second source region is disposed on the second body channel region,

the first and second body channel regions comprise P conductivity-type, and

the drift region, the Schottky semiconductor region, and the first and second source regions comprise N conductivity-type.

5. The semiconductor device of claim 4, wherein the Schottky semiconductor region includes 13th and 15th group elements of the long-form Periodic Table, and an amount per unit volume of the 15th group element is greater than that of the 13th group element in the Schottky semiconductor region,

wherein the first and second body channel regions include the 13th and the 15th group elements of the long-form Periodic Table, and an amount per unit volume of the 15th group element in the first and second body channel regions is less than that of the 13th group element in the first and second body channel regions, and

wherein the drift region adjacent to the first and second body channel regions and the Schottky semiconductor region, the first and second body channel regions, and the Schottky semiconductor region each include an equal amount per unit volume of the 15th group element.

6. The semiconductor device of claim 1, further comprising:

a first body contact region in the groove region disposed in the active region between the conductive pattern and the first body channel region; and

a second body contact region in the groove region disposed between the conductive pattern and the second body channel region, and spaced apart from the first body contact region on opposite sides of the groove region,

wherein the first and second body contact regions have a higher majority carrier concentration than in the first and second body channel regions adjacent to the first and second body contact regions.

7. The semiconductor device of claim 6, wherein the front-side conductive pattern provides ohmic contact with the first and second body contact regions and with the first and second source regions.

8-18. -18. (canceled)

19. A method of fabricating a semiconductor device, comprising:

forming a first conductivity-type semiconductor layer on a semiconductor substrate;

forming trenches in the semiconductor layer to define an active region between the trenches;

forming a shield conductive pattern and a preliminary insulating structure surrounding the shield conductive pattern in each of the trenches, wherein the preliminary insulating structure is located at a lower level than an upper surface of the active region and partially fills the trenches;

forming a body impurity region having a second conductivity-type different from the first conductivity-type by performing a body channel ion-implantation process to an upper portion of the active region,

forming an insulating structure by partially etching the preliminary insulating structure after forming the body impurity region;

forming a gate structure on the insulating structure;

forming a first conductivity-type source impurity region in the upper portion of the active region, and a groove region sequentially passing through the source impurity region and the body impurity region after forming the gate structure, wherein the groove region has a tapered sidewall, the source impurity region includes first and second source regions spaced apart from each other on opposite sides of the groove region, and the body impurity region includes first and second body channel regions spaced apart from each other on the opposite sides of the groove region; and

forming a front-side conductive pattern filling the groove region.

20. The method of claim 19, further comprising forming a Schottky semiconductor region in the active region under a bottom surface of the groove region by performing an additional ion-implantation process, before forming the front-side conductive pattern,

wherein the Schottky semiconductor region is formed by a junction of the Schottky semiconductor region and the first and second body channel regions, and is at a higher level than bottom surfaces of the first and second body channel regions.

21. The method of claim 20, wherein the semiconductor layer includes a 15th group element of the long-form Periodic Table and has N conductivity-type, and

the additional ion-implantation process comprises injecting a 13th group element of the long-form Periodic Table into the active region under the bottom surface of the groove region.

22. The method of claim 20, wherein the additional ion-implantation process comprises injecting impurity ions in a direction perpendicular to the semiconductor substrate.

23. The method of claim 19, wherein the body channel ion-implantation process comprises injecting impurity ions in a direction that is angled relative to a surface of the semiconductor substrate through which the injecting is performed.

24. The method of claim 19, further comprising forming an insulating capping pattern on the gate structure after forming the source impurity region and before forming the groove region,

wherein the insulating capping pattern comprises an etch mask used in an etching process for forming the groove region.

25. The method of claim 19, wherein the source impurity region is formed by performing a source ion-implantation process in which a 15th group element of the long-form Periodic Table is injected in a direction that is angled relative to a surface of the semiconductor substrate through which the ion-implantation process is performed.

26. A semiconductor device, comprising:

first and second vertical channel power MOSFET transistors arranged in a split-gate configuration in a semiconductor substrate;

a groove in an active region between the first and second vertical channel power MOSFET transistors;

a conductive pattern in the groove on the active region, the conductive pattern comprising a source contact for the first and second vertical channel power MOSFET transistors; and

a vertical Schottky semiconductor region embedded in the groove beneath the conductive pattern between the vertical channel power MOSFET transistors.

27. The semiconductor device according to claim 26 wherein the first and second vertical channel power MOSFET transistors arranged in the split-gate configuration operate as a single transistor.

28. The semiconductor device according to claim 26 further comprising:

a drain contact for the first and second vertical channel power MOSFET transistors beneath the groove opposite the source contact.

29. The semiconductor device according to claim 26 wherein the vertical Schottky semiconductor region and the conductive pattern comprise an embedded vertical Schottky diode forming a junction at a bottom of the groove with the active region.

30. The semiconductor device according to claim 26 wherein the vertical Schottky semiconductor region includes 13th and 15th group elements of the long-form Periodic Table, and an amount per unit volume of the 15th group element is greater than that of the 13th group element in the vertical Schottky semiconductor region.

31. The semiconductor device according to claim 29 further comprising:

first and second source regions for the respective first and second vertical channel power MOSFET transistors, the first and second source regions on opposite sides of the groove, wherein the source regions include lower most implanted regions that are above the junction.