MAGNETIC SHIELDING OF PERPENDICULAR STT-MRAM

• US 20150091109A1
• Filed: 09/27/2013
• Published: 04/02/2015
• Est. Priority Date: 09/27/2013
• Status: Active Grant

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Allinger, Robert, Hofmann, Karl, Knobloch, Klaus, Strenz, Robert
• Granted Patent: US 9,564,403 B2
• Time in Patent Office: Days
• US Class Current: 257/421
• CPC Class Codes: G11C 11/161 details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell
• CPC Class Codes: H01L 23/5225 Shielding layers formed together with wiring layers
• CPC Class Codes: H01L 23/552 Protection against radiation, e.g. light or electromagnetic waves
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H10B 61/00 Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
• CPC Class Codes: H10B 61/22 of the field-effect transistor [FET] type
• CPC Class Codes: H10N 50/01 Manufacture or treatment
• CPC Class Codes: H10N 50/10 Magnetoresistive devices
• CPC Class Codes: H10N 50/80 Constructional details

Abstract

A memory having an array of perpendicular spin-transfer torque (STT) magnetic random access memory (MRAM) cells, wherein each cell has a magnetic layer stack. A magnetic shield disposed between the cells and having a minimum height of at least the height of the magnetic layer stacks.

Claims

1. A memory comprising:

an array of perpendicular spin-transfer torque (STT) magnetic random access memory (MRAM) cells, wherein each cell has a magnetic layer stack; and

a magnetic shield disposed between the cells and having a minimum height of at least the height of the magnetic layer stacks to thereby shield the cells from memory-external magnetic fields.

2. The memory of claim 1, wherein the height of the magnetic shield is higher than the height of the magnetic layer stacks.

3. The memory of claim 1, wherein the magnetic shield is shaped to have a horizontal projection formed at at least one of its top edges.

4. The memory of claim 3, wherein at least one of the cells has an electrode formed above the magnetic layer stack, and an upper portion of the electrode has a diameter that is less than the diameter of magnetic layer stack so as to accommodate the horizontal projection of the magnetic shield.

5. The memory of claim 1, wherein the height of the magnetic shield is a maximum height possible between bit and source lines located above and below the cells.

6. The memory of claim 1, wherein the magnetic shield is located in at least one of horizontal and vertical symmetrical arrangement with respect to a free magnetic layer within the magnetic layer stack.

7. The memory of claim 1, wherein the magnetic shield has a magnetic permeability of at least 10,000.

8. The memory of claim 1, wherein the magnetic shield has a magnetic permeability of between 50,000 and 140,000.

9. The memory of claim 1, wherein the magnetic shield is comprised of one or more layers of ferromagnets.

10. The memory of claim 9, wherein the ferromagnets comprise alloys selected from the group of alloys consisting of nickel (Ni), iron (Fe), and/or cobalt (Co).

11. The memory of claim 1, wherein the magnetic shield comprises at least one of ferrimagnets and ferrites.

12. The memory of claim 1, wherein the magnetic shield comprises one or more layers of different materials.

13. The memory of claim 1, wherein the magnetic shield substantially lacks magnetic coercivity.

14. The memory of claim 1, further comprising:

a dielectric liner disposed between the cells and the magnetic shield and having a thickness large enough to provide electrical isolation.

15. The memory of claim 1, wherein a horizontal width of the magnetic shield disposed between the cells is large enough to fill space not occupied by bordering magnetic stacks and any dielectric liners.

16. A method of producing a memory comprising:

providing a perpendicular spin-transfer torque (STT) magnetic random access memory (MRAM) cell stack;

etching the cell stack to form an array of cells, wherein each cell has a magnetic layer stack; and

depositing a magnetic shield between the cells,

wherein the magnetic shield has a minimum height of at least the height of the magnetic layer stack.

17. The method of claim 16, further comprising:

before depositing the magnetic shield, depositing a dielectric liner on the array of cells; and

planarizing the magnetic shield to the dielectric liner.

18. The method of claim 16, wherein the planarizing is chemical-mechanical planarizing (CMP), and the dielectric liner is a CMP-stop.

19. The method of claim 16, wherein the magnetic shield has a height greater than the height of the magnetic layer stack.

20. A memory comprising:

an array of spin-transfer torque (STT) magnetic random access memory (MRAM) cells, wherein each cell has a magnetic layer stack; and

a magnetic shield disposed between the cells and having a minimum height of at least the height of the magnetic layer stacks to thereby shield the cells from memory-external magnetic fields.