DISPLAY DEVICE AND DRIVING METHOD THEREOF

• US 20150091883A1
• Filed: 01/22/2014
• Published: 04/02/2015
• Est. Priority Date: 10/01/2013
• Status: Active Grant

• Current Assignee: Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Original Assignee: Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Inventors: LEE, Yong Jae, LIM, Kyung-Hwa, PYUN, Ki Hyun, KIM, Yun Mi, PARK, Min Young, KIM, Sung-Jun, KIM, Ju Hyun
• Granted Patent: US 9,449,545 B2
• Time in Patent Office: Days
• US Class Current: 345/204
• CPC Class Codes: G09G 2310/0289 Details of voltage level shifters arranged for use in a driving circuit
• CPC Class Codes: G09G 2320/0252 Improving the response speed
• CPC Class Codes: G09G 3/2074 using sub-pixels
• CPC Class Codes: G09G 3/3614 Control of polarity reversal in general
• CPC Class Codes: G09G 3/3677 suitable for active matrices only

Abstract

A method of reducing a time for switching a gate line driving signal of display device having plural gate lines from a level that is less than a full gate-on level to the gate-on level is disclosed. The method may include: during a gate line pre-charging period of a respective gate line, causing the gate line driving signal to be at the full gate-on level; during a corresponding gate line main-charging period that follows the pre-charging period, causing the gate line driving signal of to be at the full gate-on level; and during an interposed period that is interposed between the gate line pre-charging period and its corresponding gate line main-charging period, causing the gate line driving signal to be at an intermediate level that is between the full gate-on level and an opposed gate-off level.

Claims

1. A driving method which drives a display device having a display panel comprising a plurality of gate lines and having a gate lines driver configured to output respective gate signals to the plurality of gate lines respectively, the method comprising:

receiving, by the gate lines driver, at least one gate clock signal and at least one output enable signal, the output enable signal having a first level representing a first digital state and a second level representing a second digital state;

outputting, by the gate lines driver, a first gate line driving voltage or a second gate line driving voltage different from the first gate line driving voltage when the at least one output enable signal is at the first level; and

outputting, by the gate lines driver, a third gate line driving voltage having a level between that of the first and second gate line driving voltages when the at least one output enable signal is at the second level.

2. The method of claim 1, wherein:

the first gate line driving voltage includes a transistor-saturating gate-on voltage, and

the second gate line driving voltage includes a gate-off voltage.

3. The method of claim 2, wherein:

the third gate line driving voltage is at least approximately equal to an average of the gate-on voltage and of the gate-off voltage.

4. The method of claim 3, wherein:

the gate lines driver includes a level shifter and the level shifter comprises;

a first transistor and a second transistor that are both controlled by a first control signal, and

a third transistor that is controlled by a second control signal separate from the first control signal,

wherein the first control signal is synchronized with the at least one gate clock signal, and

the second control signal is synchronized with the at least one output enable signal.

5. The method of claim 4, wherein:

the first transistor is connected between the gate-on voltage and an output terminal providing the first, second and third gate line driving voltages, and

the second transistor is connected between the gate-off voltage and the output terminal.

6. The method of claim 5, wherein:

a channel type of the first transistor is opposite to a channel type of the second transistor, and

a channel type of the third transistor is identical to the channel type of the second transistor.

7. The method of claim 6, wherein:

the third transistor is connected between the output terminal and the gate-off voltage.

8. The method of claim 7, wherein:

the outputting of the first gate line driving voltage or the second gate line driving voltage when the output enable signal is the first level comprises outputting the gate-on voltage during a pre-charging period immediately before a period when the output enable signal is the second level and also outputting the gate-on voltage during a main charging period immediately after the period when the output enable signal is the second level.

9. The method of claim 5, wherein:

a channel type of the first transistor is opposite to a channel type of the second transistor, and

a channel type of the third transistor is identical to the channel type of the first transistor.

10. The method of claim 9, wherein:

the third transistor is connected between the output terminal and the gate-on voltage.

11. The method of claim 10, wherein:

the outputting of the first gate line driving voltage or the second gate line driving voltage when the output enable signal is the first level comprises outputting the gate-on voltage during a pre-charging period immediately before a period when the output enable signal is the second level and also outputting the gate-on voltage during a main charging period immediately after the period when the output enable signal is the second level.

12. A display device, comprising:

a display panel comprising a plurality of gate lines; and

a gate lines driver configured to receive a gate clock signal and an output enable signal, the output enable signal having a first level and a second level, the gate lines driver being further configured to output respective gate line driving signals to respective ones of the plurality of gate lines,

wherein the gate lines driver comprises a level shifter configured to output a first gate line driving voltage or a second gate line driving voltage different from the first gate line driving voltage when the output enable signal is the first level, and to output a third gate line driving voltage having a level between those of the first and second gate line driving voltages when the output enable signal is the second level.

13. The display device of claim 12, wherein:

the first gate line driving voltage includes a gate-on voltage, and

the second gate line driving voltage includes a gate-off voltage.

14. The display device of claim 13, wherein:

the third gate line driving voltage is an average of the gate-on voltage and the gate-off voltage.

15. The display device of claim 14, wherein:

the level shifter comprises a first transistor and a second transistor that are controlled by a first control signal, and a third transistor that is controlled by a second control signal separate from the first control signal,

the first control signal is synchronized with the gate clock signal,

the second control signal is synchronized with the output enable signal,

the first transistor is connected between the gate-on voltage and an output terminal which outputs the first, second and third gate line driving voltages, and

the second transistor is connected between the gate-off voltage and the output terminal.

16. The display device of claim 15, wherein:

a channel type of the first transistor is opposite to a channel type of the second transistor,

a channel type of the third transistor is identical to the channel type of the second transistor, and

the third transistor is connected between the output terminal and the gate-off voltage.

17. The display device of claim 16, wherein:

the gate lines driver outputs to a respective one of the plurality of gate lines, the gate-on voltage during a pre-charging period immediately before a period when the output enable signal is the second level and also outputs the gate-on voltage to the respective gate line during a main charging period which occurs immediately after the period when the output enable signal is the second level.

18. The display device of claim 17, wherein:

the display panel further comprises;

a first data line and a second data line extended in a first direction and adjacent to each other; and

a plurality of pixels connected to the first and second data lines and the plurality of gate lines, and

a plurality of pixels arranged in the first direction are alternately connected to the first and second data lines.

19. The display device of claim 15, wherein:

a channel type of the first transistor is opposite to a channel type of the second transistor,

a channel type of the third transistor is identical to the channel type of the first transistor, and

the third transistor is connected between the output terminal and the gate-on voltage.

20. The display device of claim 19, wherein:

the gate lines driver outputs the gate-on voltage during a pre-charging period immediately before a period when the output enable signal is the second level and also outputs the gate-on voltage during a main charging period immediately after the period when the output enable signal is the second level.

21. The display device of claim 20, wherein:

the display panel further comprises;

a first data line and a second data line extended in a first direction and adjacent to each other; and

a plurality of pixels connected to the first and second data lines and the plurality of gate lines, and

a plurality of pixels arranged in the first direction are alternately connected to the first and second data lines.

22. A method of reducing a time for switching a gate line driving signal of display device having plural gate lines from a level that is less than a full gate-on level to the gate-on level, the method comprising:

during a gate line pre-charging period of respective gate line, causing the gate line driving signal of the respective gate line to be at the full gate-on level;

during a corresponding gate line main-charging period that follows the pre-charging period, causing the gate line driving signal of the respective gate line to be at the full gate-on level; and

during an interposed period that is interposed between the gate line pre-charging period and its corresponding gate line main-charging period, causing the gate line driving signal of the respective gate line to be at an intermediate level that is between the full gate-on level and an opposed gate-off level;

wherein the full gate-on level causes corresponding pixel switching elements of the display device to which that level is applied to be in a low resistance, saturated mode;

wherein the gate-off level causes the corresponding pixel switching elements of the display device to which that level is applied to be in a sub-threshold turned-off mode;

wherein the intermediate level causes the corresponding pixel switching elements of the display device to which that level is applied to be in an intermediate resistive mode having a resistance between that of turned-off mode and that of the low resistance, saturated mode; and

wherein a time for transitioning the gate line driving signal from the intermediate level to the full gate-on level is substantially less than a time for transitioning the gate line driving signal from the gate-off level to the full gate-on level.

23. The method of claim 22 wherein:

the gate lines of the display device are sequentially driven in accordance with predetermined horizontal scan periods; and

for each gate line, its respective gate line pre-charging period occurs during a first horizontal scan period, its respective gate line interposed period occurs during a second horizontal scan period immediately following the first horizontal scan period, and its respective gate line main-charging period occurs during a third horizontal scan period immediately following the second horizontal scan period.

24. The method of claim 23 wherein:

the display device is driven in accordance with at least one of a dot polarity inversion method, a row polarity inversion method and a column polarity inversion method.