FLASH MEMORY SYSTEM ENDURANCE IMPROVEMENT USING TEMPERATURE BASED NAND SETTINGS

• US 20150092488A1
• Filed: 09/27/2013
• Published: 04/02/2015
• Est. Priority Date: 09/27/2013
• Status: Active Application

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Wakchaure, Yogesh, Pangal, Kiran, Guo, Xin
• Application Number:
  US14/040,239
• Publication Number:
  US 20150092488A1
• Time in Patent Office: Days
• US Class Current: 365/185.03
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/3454 Arrangements for verifying correct programming or for detecting overprogrammed cells
• CPC Class Codes: G11C 16/349 Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles
• CPC Class Codes: G11C 7/04 with means for avoiding disturbances due to temperature effects

Abstract

Methods and apparatus to improve flash memory system endurance using temperature based flash memory settings are described. In one embodiment, memory controller logic applies one of a first trim profile or a second trim profile to a flash memory storage device based at least partially on a comparison of a threshold temperature value and a sensed temperature of the flash memory storage device. Other embodiments are also disclosed and claimed.

Claims

1. An apparatus comprising:

memory controller logic to apply one of a first trim profile or a second trim profile to a flash memory storage device based at least partially on a comparison of a threshold temperature value and a sensed temperature of the flash memory storage device.

2. The apparatus of claim 1, further comprising a temperature sensor, thermally proximate to the flash memory storage device, to detect the sensed temperature.

3. The apparatus of claim 1, wherein the flash memory storage device is to comprise a NAND flash memory or a NOR flash memory.

4. The apparatus of claim 1, wherein the flash memory storage device is to be programmed based at least partially on one or more Multi Level Cell (MLC) voltage levels.

5. The apparatus of claim 1, wherein the memory controller logic is to apply the first trim profile to the flash memory storage device based at least partially on a subsequent comparison of the threshold temperature value and a subsequent sensed temperature of the flash memory storage device, wherein the subsequent sensed temperature value of the flash memory storage device is to be higher than the sensed temperature of the flash memory storage device.

6. The apparatus of claim 1, wherein the memory controller logic is to apply a third trim profile to the flash memory storage device based at least partially on a subsequent comparison of a subsequent threshold temperature value and a subsequent sensed temperature of the flash memory storage device.

7. The apparatus of claim 1, wherein the memory controller logic is to perform one or more of the following adjustments to the first or second trim profiles:

trade a data retention margin for program disturb (PD), erase deeper to improve a first edge margin, dynamically change to Single Level Cell (SLC) mode, optimize trim settings for lower temperatures, provide slower program trims, or dynamically adjust read voltage.

8. The apparatus of claim 1, wherein one or more processor cores are coupled to the memory controller logic to access data stored in the flash memory storage device.

9. A method comprising:

applying one of a first trim profile or a second trim profile to a flash memory storage device based at least partially on a comparison of a threshold temperature value and a sensed temperature of the flash memory storage device.

10. The method of claim 9, further comprising detecting the sensed temperature at a temperature sensor that is thermally proximate to the flash memory storage device.

11. The method of claim 9, wherein the flash memory storage device comprises a NAND flash memory or a NOR flash memory.

12. The method of claim 9, further comprising programming the flash memory storage device based at least partially on one or more Multi Level Cell (MLC) voltage levels.

13. The method of claim 9, further comprising applying the first trim profile to the flash memory storage device based at least partially on a subsequent comparison of the threshold temperature value and a subsequent sensed temperature of the flash memory storage device, wherein the subsequent sensed temperature value of the flash memory storage device is higher than the sensed temperature of the flash memory storage device.

14. The method of claim 9, further comprising applying a third trim profile to the flash memory storage device based at least partially on a subsequent comparison of a subsequent threshold temperature value and a subsequent sensed temperature of the flash memory storage device.

15. The method of claim 9, further comprising performing one or more of the following adjustments to the first or second trim profiles:

trade a data retention margin for program disturb (PD), erase deeper to improve a first edge margin, dynamically change to Single Level Cell (SLC) mode, optimize trim settings for lower temperatures, provide slower program trims, or dynamically adjust read voltage.

16. A computer-readable medium comprising one or more instructions that when executed on a processor configure the processor to perform one or more operations to:

apply one of a first trim profile or a second trim profile to a flash memory storage device based at least partially on a comparison of a threshold temperature value and a sensed temperature of the flash memory storage device.

17. The computer-readable medium of claim 16, further comprising one or more instructions that when executed on the processor configure the processor to perform one or more operations to cause detection of the sensed temperature at a temperature sensor that is thermally proximate to the flash memory storage device.

18. The computer-readable medium of claim 16, wherein the flash memory storage device comprises a NAND flash memory or a NOR flash memory.

19. The computer-readable medium of claim 16, further comprising one or more instructions that when executed on the processor configure the processor to perform one or more operations to cause programming of the flash memory storage device based at least partially on one or more Multi Level Cell (MLC) voltage levels.

20. The computer-readable medium of claim 16, further comprising one or more instructions that when executed on the processor configure the processor to perform one or more operations to cause application of the first trim profile to the flash memory storage device based at least partially on a subsequent comparison of the threshold temperature value and a subsequent sensed temperature of the flash memory storage device, wherein the subsequent sensed temperature value of the flash memory storage device is higher than the sensed temperature of the flash memory storage device.

21. The computer-readable medium of claim 16, further comprising one or more instructions that when executed on the processor configure the processor to perform one or more operations to cause application of a third trim profile to the flash memory storage device based at least partially on a subsequent comparison of a subsequent threshold temperature value and a subsequent sensed temperature of the flash memory storage device.

22. The computer-readable medium of claim 16, further comprising one or more instructions that when executed on the processor configure the processor to perform one or more operations to cause performance of one or more of the following adjustments to the first or second trim profiles:

trade a data retention margin for program disturb (PD), erase deeper to improve a first edge margin, dynamically change to Single Level Cell (SLC) mode, optimize trim settings for lower temperatures, provide slower program trims, or dynamically adjust read voltage.

23. A system comprising:

a NAND flash memory device having a plurality of memory cells;

a processor to access the NAND flash memory device; and

NAND flash memory controller logic, coupled to the NAND flash memory device, to apply one of a first trim profile or a second trim profile to the NAND flash memory device based at least partially on a comparison of a threshold temperature value and a sensed temperature of the NAND flash memory device.

24. The system of claim 23, further comprising a temperature sensor, thermally proximate to the NAND flash memory device, to detect the sensed temperature.

25. The system of claim 23, wherein the NAND flash memory device is to be programmed based at least partially on one or more Multi Level Cell (MLC) voltage levels.