FLASH MEMORY REFERENCE VOLTAGE DETECTION WITH TRACKING OF CROSS-POINTS OF CELL VOLTAGE DISTRIBUTIONS USING HISTOGRAMS

• US 20150092489A1
• Filed: 10/21/2013
• Published: 04/02/2015
• Est. Priority Date: 09/27/2013
• Status: Active Grant

• Current Assignee: Seagate Technology LLC (Seagate Technology Holdings Plc)
• Original Assignee: LSI Corporation (Broadcom, Inc.)
• Inventors: Wu, Yunxiang, Alhussien, Abdel-Hakim, Chen, Zhengang, Sankaranarayanan, Sundararajan, Haratsch, Erich F.
• Granted Patent: US 9,036,413 B2
• Time in Patent Office: Days
• US Class Current: 365/185.03
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/349 Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles
• CPC Class Codes: G11C 29/021 in voltage or current generators
• CPC Class Codes: G11C 29/028 with adaption or trimming of parameters
• CPC Class Codes: G11C 7/14 Dummy cell management; Sense reference voltage generators

Abstract

Cross-points of flash memory cell voltage distributions are determined by reading data from a portion of the flash memory two or more times using two or more different candidate reference voltages and determining corresponding decision patterns. The frequency of occurrence of the decision patterns in the data read from the flash memory is used to conceptually construct a histogram. The histogram is used to estimate the cross-points. Employing decision patterns enables multiple cross-point voltages to be determined with a minimum of read operations.

Claims

1. A method for flash memory controller operation, comprising:

reading data from a portion of a flash memory a plurality of times using a plurality of different candidate reference voltages, each time reading data from the portion of the flash memory using a different candidate reference voltage from all other times, the plurality of different candidate reference voltages distributed over a voltage range, the voltage range centered on an estimated mid-point between a pair of adjacent target cell voltages;

determining a plurality of decision patterns, each decision pattern corresponding to a voltage region bordering one of the candidate reference voltages;

counting occurrences of each of the plurality of decision patterns in the data read from the portion of the flash memory;

determining one or more of the decision patterns having a minimum of occurrences;

determining a cross-point voltage corresponding to a mid-point of one or more voltage regions corresponding to the one or more decision patterns determined to have a minimum of occurrences; and

providing an indication of the cross-point voltage to a read data detector.

2. The method of claim 1, wherein:

reading data from a portion of a flash memory a plurality of times using a plurality of different candidate reference voltages comprises reading data from a portion of a flash memory N times using N different candidate reference voltages, where N is an integer greater than one; and

determining a plurality of decision patterns comprises determining N+1 decision patterns.

3. The method of claim 1, wherein:

reading data from a portion of a flash memory a plurality of times using a plurality of different candidate reference voltages comprises reading data from a portion of a flash memory N times using N different pairs of candidate reference voltages, where N is an integer greater than one; and

determining a plurality of decision patterns comprises determining 2N decision patterns.

4. The method of claim 1, wherein the method is performed two times to determine three cross-point voltages of a multi-level cell (MLC) flash memory having four target cell voltages.

5. The method of claim 1, wherein reading data from a portion of a flash memory a plurality of times comprises reading data using the estimated mid-point between two target cell voltages and reading data using incrementally higher and lower candidate reference voltages from the estimated mid-point.

6. The method of claim 1, wherein all voltage regions are equal to each other in width.

7. The method of claim 3, wherein N=8.

8. A flash memory controller, comprising:

a buffer memory;

a processing system comprising;

read logic for reading data into the buffer memory from a portion of a flash memory a plurality of times using a plurality of different candidate reference voltages, each time reading data from the portion of the flash memory using a different candidate reference voltage from all other times, the plurality of different candidate reference voltages distributed over a voltage range, the voltage range centered on an estimated mid-point between a pair of adjacent target cell voltages;

decision pattern logic for determining a plurality of decision patterns, each decision pattern corresponding to a voltage region bordering one of the candidate reference voltages;

histogram logic for counting occurrences of each of the plurality of decision patterns in the data read from the portion of the flash memory, the decision pattern logic further determining one or more decision patterns having a minimum of occurrences;

cross-point estimation logic for determining a cross-point voltage corresponding to a mid-point of one or more voltage regions corresponding to the one or more decision patterns determined to have a minimum of occurrences; and

read data detection logic for receiving from the cross-point estimation logic an indication of the cross-point voltage.

9. The flash memory controller of claim 8, wherein:

the read logic reads data from the portion of a flash memory N times using N different candidate reference voltages, where N is an integer greater than one; and

the decision pattern logic determines N+1 decision patterns.

10. The flash memory controller of claim 8, wherein:

the read logic reads data from the portion of a flash memory N times using N different pairs of candidate reference voltages, where N is an integer greater than one; and

the decision pattern logic determines 2N decision patterns.

11. The flash memory controller of claim 8, wherein three cross-point voltages of a multi-level cell (MLC) flash memory having four target cell voltages are determined.

12. The flash memory controller of claim 8, wherein reading data into the buffer memory from a portion of a flash memory a plurality of times comprises reading data using the estimated mid-point between two target cell voltages and reading data using incrementally higher and lower candidate reference voltages from the estimated mid-point.

13. The flash memory controller of claim 8, wherein all voltage regions are equal to each other in width.

14. The flash memory controller of claim 10, wherein N=8.

15. A computer program product for flash memory control, the computer program product comprising a computer-readable medium having stored therein in computer-executable non-transitory form instructions that, when executed on a processing system of a flash memory controller, cause the processing system to effect a method comprising:

reading data from a portion of a flash memory a plurality of times using a plurality of different candidate reference voltages, each time reading data from the portion of the flash memory using a different candidate reference voltage from all other times, the plurality of different candidate reference voltages distributed over a voltage range, the voltage range centered on an estimated mid-point between a pair of adjacent target cell voltages;

determining a plurality of decision patterns, each decision pattern corresponding to a voltage region bordering one of the candidate reference voltages;

counting occurrences of each of the plurality of decision patterns in the data read from the portion of the flash memory;

determining one or more decision patterns having a minimum of occurrences;

determining a cross-point voltage corresponding to a mid-point of one or more voltage regions corresponding to the one or more decision patterns determined to have a minimum of occurrences; and

providing an indication of the cross-point voltage to a read data detector.

16. The computer program product of claim 15, wherein:

reading data from a portion of a flash memory a plurality of times using a plurality of different candidate reference voltages comprises reading data from a portion of a flash memory N times using N different candidate reference voltages, where N is an integer greater than one; and

determining a plurality of decision patterns comprises determining N+1 decision patterns.

17. The computer program product of claim 15, wherein the instructions cause the processing system to effect the method two times to determine three cross-point voltages of a multi-level cell (MLC) flash memory having four target cell voltages.

18. The computer program product of claim 15, wherein reading data from a portion of a flash memory a plurality of times comprises reading data using the estimated mid-point between two target cell voltages and reading data using incrementally higher and lower candidate reference voltages from the estimated mid-point.

19. The computer program product of claim 15, wherein all voltage regions are equal to each other in width.

20. The computer program product of claim 15, wherein N=8.