QUEUE CREDIT MANAGEMENT

• US 20150092546A1
• Filed: 12/08/2014
• Published: 04/02/2015
• Est. Priority Date: 07/11/2013
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: BARATAM, Prakash B., VANDERPOOL, Brian T.
• Granted Patent: US 9,455,926 B2
• Time in Patent Office: Days
• US Class Current: 370/230
• CPC Class Codes: H04L 47/39 Credit based
• CPC Class Codes: H04L 47/527 Quantum based scheduling, e.g. credit or deficit based scheduling or token bank
• CPC Class Codes: H04L 49/90 Buffering arrangements

Abstract

To prevent buffer overflow, a receiving entity may use credits to control the total amount of packets any single transmitting entity can forward. Once the assigned credits are spent, the transmitting entity cannot send data portions to the receiving entity until additional credits are provided. However, the logic in the receiving entity may be designed to manage a maximum number of credits that is less than the capacity of the buffer in the transmitting entity. For example, the receiving entity is designed to manage a maximum of eight credits but the buffer has room for twelve data portions. To use the buffer efficiently, the transmitting entity may identify when extra buffer storage is available and provide additional credits. In addition, the transmitting entity may control when the credits are provided such that the receiving entity is not allocated more credits that it was designed to manage.

Claims

1. A method comprising:

providing a number of credits to a first module not in excess of a maximum number of credits the first module is designed to manage, wherein the first module maintains a credit count that is decreased each time a data packet is transmitted from the first module to a second module;

storing a plurality of received data packets from the first module in a memory buffer in the second module, the memory buffer having predefined memory locations dedicated to storing data packets received only from the first module, wherein the number of memory locations exceeds the maximum number of credits the first module is designed to manage; and

upon determining that the credit count of the first module is less than the maximum number of credits and that there is available space in the memory locations, providing an extra credit to the first module, thereby increasing the credit count.

2. The method of claim 1, further comprising:

performing arbitration to determine if one of the received data packets stored in the memory buffer is to be forward on an output link of the second module;

if so;

forwarding the one received data packet on the output link, and

providing a refund credit to the first module, thereby increasing the credit count.

3. The method of claim 1, further comprising, upon start up of the second module, setting the credit count equal to the maximum number of credits the first module is designed to manage, wherein the maximum number of credits the first module is based on at least one of testing and verifying a design of the first module.

4. The method of claim 1, further comprising:

determining a total number of extra credits to provide to the first module by subtracting the total of number of data packets that can be stored in the plurality of memory locations of the memory buffer by the maximum number of credits the first module is designed to manage; and

providing the total number of extra credits to the first module such that the credit count does not exceed the maximum number of credits the first module is designed to manage.

5. The method of claim 4, further comprising, providing the total number of extra credits to the first module after determining that the credit count is zero.

6. The method of claim 1, wherein the first module comprises a first switch and the second module comprises a second switch, wherein the first module is mounted on a first substrate and the second module is mounted on a second substrate physically separate from the first substrate.

7. The method of claim 6, wherein the first switch is coupled to the second switch by a transmit link and a receive link.