INTEGRATED CIRCUIT DEVICES INCLUDING FINFETS AND METHODS OF FORMING THE SAME

• US 20150093868A1
• Filed: 09/18/2014
• Published: 04/02/2015
• Est. Priority Date: 09/27/2013
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Obradovic, Borna J., Rodder, Mark S., Bowen, Robert C.
• Granted Patent: US 9,178,045 B2
• Time in Patent Office: Days
• US Class Current: 438/283
• CPC Class Codes: H01L 21/26506 in group IV semiconductors
• CPC Class Codes: H01L 21/26513 of electrically active species
• CPC Class Codes: H01L 21/266 using masks H01L21/26586 takes precedence
• CPC Class Codes: H01L 21/30604 Chemical etching
• CPC Class Codes: H01L 21/308 using masks H01L21/3063, H01L21/3065 take precedence
• CPC Class Codes: H01L 21/3086 characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
• CPC Class Codes: H01L 21/823431 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823821 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/16 including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
• CPC Class Codes: H01L 29/161 including two or more of the elements provided for in group H01L29/16 , e.g. alloys H01L29/1604 takes precedence
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7848 the means being located in the source/drain region, e.g. SiGe source and drain
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

Integrated circuit devices including fin field-effect transistors (finFETs) and methods of forming the same are provided. The methods may include forming a fin-shaped channel region including germanium on a substrate and forming a source/drain region adjacent the channel region on the substrate. The methods may further include forming a barrier layer contacting sidewalls of the channel region and the source/drain region, and the barrier layer may include Si_xGe_1-x, and x may be in a range of about 0.05 to about 0.2.

Claims

1. A method of forming a finFET, the method comprising:

forming a fin-shaped channel region comprising germanium on a substrate;

forming a source/drain region adjacent the channel region on the substrate;

forming a barrier layer contacting sidewalls of the channel region and the source/drain region, wherein the barrier layer comprises Si_xGe_1-x, and x is in a range of about 0.05 to about 0.2.

2. The method of claim 1, wherein a germanium concentration in the channel region is greater than a germanium concentration in the barrier layer.

3. The method of claim 1, wherein:

forming the channel region comprises forming the channel region comprising Si_1-yGe_y, and y is in a range of about 0.8 to about 1; and

forming the source/drain region comprises forming a portion of the source/drain region comprising substantially pure germanium.

4. The method of claim 3, wherein:

a germanium concentration in the channel region is greater than a germanium concentration in the barrier layer; and

a germanium concentration in the source/drain region is substantially equal to or greater than the germanium concentration in the barrier layer.

6. The method of claim 1, wherein:

forming the channel region comprises forming the channel region comprising Si_1-yGe_y, and y is in a range of about 0.85 to about 1; and

forming the source/drain region comprises forming a portion of the source/drain region comprising substantially pure silicon.

7. The method of claim 6, wherein a germanium concentration in the channel region is greater than a germanium concentration in the barrier layer.

9. The method of claim 1, wherein forming the channel region and the barrier layer comprises:

forming a preliminary channel region on the substrate;

forming a mask pattern on the preliminary channel region;

etching the preliminary channel region using the mask pattern as an etching mask to form the channel region; and

epitaxially growing the barrier layer using the channel region as a seed layer.

12. The method of claim 1, wherein forming the channel region and the barrier layer comprises:

forming a preliminary channel region on the substrate;

forming a first mask pattern on a first portion of the preliminary channel region;

implanting silicon ions into the preliminary channel region using the first mask pattern as an implantation blocking mask;

forming a second mask pattern on the first portion of the preliminary channel region after implanting the silicon ions; and

etching the preliminary channel region using the second mask pattern as an etching mask to form the channel region and the barrier layer.

15. The method of claim 1, wherein:

forming the source/drain region comprises forming a first source/drain region adjacent a first sidewall of the channel region such that the barrier layer contacts the first sidewall of the channel region and a sidewall of the first source/drain region; and

the method further comprises forming a second source/drain region contacting a second sidewall of the channel region opposite the first sidewall of the channel region.

17. The method of claim 1, wherein a width of the barrier layer in a direction from the channel region to the source/drain region is about 10 nm.

18. The method of claim 1, further comprising forming a gate electrode overlying the channel region, wherein a sidewall of the barrier layer contacting the sidewall of the channel region is substantially aligned to a sidewall of the gate electrode such that a junction is formed in the barrier layer.

5. (canceled)

8. (canceled)

10. (canceled)

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13. (canceled)

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16. (canceled)

19. A method of forming a finFET, the method comprising:

forming a fin-shaped channel region comprising germanium on a substrate;

forming a source/drain region on a sidewall of the channel region on the substrate; and

forming a barrier layer between the sidewall of the channel region and a sidewall of the source/drain region, wherein;

the barrier layer comprises silicon and germanium; and

a germanium concentration in the barrier layer is less than a germanium concentration in the channel region.

20. The method of claim 19, wherein forming the barrier layer comprises forming the barrier layer comprising Si_xGe_1-x, and x is in a range of about 0.05 to about 0.2.

25. The method of claim 19, wherein:

forming the channel region comprises forming the channel region comprising Si_1-yGe_y, and y is in a range of about 0.8 to about 1; and

forming the source/drain region comprises forming a portion of the source/drain region comprising substantially pure germanium.

27. The method of claim 25, wherein:

a germanium concentration in the channel region is greater than a germanium concentration in the barrier layer; and

a germanium concentration in the source/drain region is substantially equal to or greater than the germanium concentration in the barrier layer.

29. The method of claim 19, wherein:

forming the channel region comprises forming the channel region comprising Si_1-yGe_y, and y is in a range of about 0.85 to about 1; and

forming the source/drain region comprises forming a portion of the source/drain region comprising substantially pure silicon.

31. The method of claim 29, wherein a germanium concentration in the channel region is greater than a germanium concentration in the barrier layer.

33. The method of claim 19, wherein:

forming the source/drain region comprises forming a first source/drain region on a first sidewall of the channel region such that the barrier layer is disposed between the first sidewall of the channel region and a sidewall of the first source/drain region; and

the method further comprises forming a second source/drain region contacting a second sidewall of the channel region opposite the first sidewall of the channel region.

34. The method of claim 19, wherein a width of the barrier layer in a direction from the channel region to the source/drain region is about 10 nm.

35. The method of claim 19, further comprising forming a gate electrode overlying the channel region, wherein a sidewall of the barrier layer facing the sidewall of the channel region is substantially aligned to a sidewall of the gate electrode such that a junction is formed in the barrier layer.

21-24. -24. (canceled)

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36-46. -46. (canceled)