Methods of Fabricating Semiconductor Devices

• US 20150093897A1
• Filed: 06/09/2014
• Published: 04/02/2015
• Est. Priority Date: 10/02/2013
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Cha-Won Koh, Hyo-Sung Lee, Hyun-Woo Kim, Jeon-Ll Lee
• Inventors: Koh, Cha-Won, Kim, Hyun-Woo, Lee, Jeon-ll, Lee, Hyo-Sung
• Granted Patent: US 9,147,687 B2
• Time in Patent Office: Days
• US Class Current: 438/671
• CPC Class Codes: G03F 7/0002 Lithographic processes using patterning methods other than those involving the exposure to radiation, e.g. by stamping
• CPC Class Codes: H01L 21/283 Deposition of conductive or insulating materials for electrodes conducting electric current
• CPC Class Codes: H01L 21/3065 Plasma etching; Reactive-ion etching
• CPC Class Codes: H01L 21/31144 using masks
• CPC Class Codes: H01L 21/32139 using masks
• CPC Class Codes: H10B 20/60 Peripheral circuit regions
• CPC Class Codes: H10B 41/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 41/50 characterised by the boundary region between the core region and the peripheral circuit region
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/50 characterised by the boundary region between the core and peripheral circuit regions

Abstract

Semiconductor devices and methods of fabricating the same are provided. The methods include preparing a template having a three dimensional (3D) stair type structure formed in intaglio, forming an imprint pattern having the stair type structure using the template, and simultaneously forming stair type patterns on a substrate using the imprint pattern.

Claims

1. A method of fabricating a semiconductor device, the method comprising:

preparing a template having a three dimensional (3D) stair type structure formed in intaglio;

forming an imprint pattern having the stair type structure using the template; and

simultaneously forming a stair type pattern on a substrate using the imprint pattern.

2. The method of claim 1, wherein forming the imprint pattern comprises using a nano-imprint process.

3. The method of claim 1, wherein forming the stair type pattern on the substrate comprises using a dry etching process.

4. The method of claim 3, wherein the dry etching process is a plasma etching process.

5. The method of claim 1, wherein the stair type structure includes three or more layers.

6. The method of claim 1, wherein the stair type pattern comprises stairs having constant heights and widths.

7. The method of claim 1, wherein the substrate has an insulation film and a conductive film alternately stacked.

8. The method of claim 7, wherein the stair type pattern comprises the insulation film and the conductive film in each layer.

9. A method of fabricating a semiconductor device, the method comprising:

preparing a template having a three dimensional (3D) stair type structure formed in intaglio, the stair type structure including first to nth layers;

forming an imprint pattern having the stair type structure using the template;

forming a first layer on the substrate using the imprint pattern as a mask;

forming a second layer on the substrate using the imprint pattern as a mask after removing the first layer of the imprint pattern; and

sequentially forming the third to nth layers on the substrate by sequentially removing the second to nth layers of the imprint pattern using the imprint pattern as a mask.

10. The method of claim 9, wherein forming the imprint pattern is performed using a nano-imprint process.

11. The method of claim 9, wherein forming the first to nth layers on the substrate comprises using photolithography.

12. The method of claim 9, wherein the stair type structure includes three or more layers.

13. The method of claim 9, wherein the first to nth layers formed on the substrate have constant heights and widths.

14. The method of claim 9, wherein the substrate has an insulation film and a conductive film alternately stacked.

15. The method of claim 14, wherein each layer of the first to nth layers comprises the insulation film and the conductive film.

16. A method of fabricating a semiconductor device, comprising:

forming an imprint pattern having a three dimensional (3D) stair type structure using a template that mirrors the 3D stair type structure, wherein the 3D stair type structure comprises at least three stairs of similar height and width; and

forming a stair type pattern on a substrate using the imprint pattern, wherein each of the at least three stairs of the stair type pattern is formed simultaneously.

17. The method of claim 16, wherein forming the stair type pattern comprises forming the stair type pattern using one cycle of a nano-imprint process.

18. The method of claim 17, wherein forming the stair type pattern comprises plasma etching through the imprint pattern.

19. The method of claim 18, wherein the substrate has an insulation film and a conductive film alternately stacked, and wherein forming the stair type pattern comprises forming each of the at least three stairs of the stair type pattern similar in height to a combined height of a layer of the insulation film and an adjacent layer of the conductive film.

20. The method of claim 19, wherein forming the imprint pattern comprises pressing the template on anti-adhesion layer coated on a resin layer coated on an uppermost layer of the conductive film and curing the resin layer.