Method for Specifying Packet Address Range Cacheability

• US 20150095582A1
• Filed: 09/30/2013
• Published: 04/02/2015
• Est. Priority Date: 09/30/2013
• Status: Abandoned Application

• Current Assignee: Avaya Incorporated
• Original Assignee: Avaya Incorporated
• Inventors: Assarpour, Hamid
• Application Number:
  US14/041,751
• Publication Number:
  US 20150095582A1
• Time in Patent Office: Days
• US Class Current: 711/133
• CPC Class Codes: G06F 12/0888 using selective caching, e.g. bypass
• CPC Class Codes: G06F 12/12 Replacement control
• CPC Class Codes: G06F 2212/1016 Performance improvement
• CPC Class Codes: H04L 45/742 Route cache; Operation thereof
• CPC Class Codes: H04L 45/745 Address table lookup; Address filtering
• CPC Class Codes: H04L 45/7452 Multiple parallel or consecutive lookup operations lookup operation involving Bloom filters H04L45/7459

Abstract

A method for specifying packet address range cacheability is provided. The method includes passing a memory allocation request from an application running on a network element configured to implement packet forwarding operations to an operating system of a network element, the memory allocation request including a table ID associated with an application table to be stored using the memory allocation. The method also includes allocating a memory address range by the operating system to the application in response to the memory allocation request, and inserting an entry in a cacheability register, the entry including the table ID included in the memory allocation request and the memory address range allocated in response to the memory allocation request.

Claims

1. A method for specifying packet address range cacheability, the method comprising the steps of:

passing a memory allocation request from an application, running on a network element configured to implement packet forwarding operations, to an operating system of the network element, the memory allocation request including a table ID associated with an application table to be stored using the memory allocation;

allocating a memory address range by the operating system to the application in response to the memory allocation request; and

inserting an entry in a cacheability register, the entry including the table ID included in the memory allocation request and the memory address range allocated in response to the memory allocation request.

2. The method of claim 1, wherein the memory allocation request further includes a memory allocation size and an application ID.

3. The method of claim 1, further comprising setting a cacheability indicator for the entry in the cacheability register, the cacheability indicator specifying whether a cache miss associated with a memory address within the allocated memory address range will trigger a cache update operation.

4. The method of claim 3, wherein the step of setting the cacheability indicator is derived from information contained in the memory allocation request.

5. The method of claim 3, further comprising receiving first cacheability information associated with the table ID from a management application, and wherein the step of setting the cacheability indicator is derived from the first cacheability information.

6. The method of claim 5, further comprising the steps of:

receiving second cacheability information associated with the table ID from the management application; and

changing the cacheability indicator for the entry in the cacheability register, based on the second information.

7. The method of claim 6, wherein the first information comprises an indication that the memory allocation associated with the table ID is cacheable such that a cache miss associated with a memory address within the allocated memory address range will trigger a cache update operation.

8. The method of claim 7, wherein the second information comprises an indication that the memory allocation associated with the table ID is not cacheable such that a cache miss associated with a memory address within the allocated memory address range will not trigger a cache update operation.

9. The method of claim 3, wherein the cache update operation comprises execution of a cache replacement algorithm to selectively update the cache.

10. A memory allocation request operating system call, comprising:

an application ID;

a table ID; and

a memory allocation size.

11. The memory allocation request operating system call of claim 10, wherein the memory allocation request operating system call further comprises a cacheability indication associated with the table ID.

12. A network element, comprising:

a network processing unit;

packet forwarding hardware under the control of the network processing unit;

a cache associated with the network processing unit;

a physical memory connected to the network processing unit and not implemented as part of the cache;

a plurality of packet address tables stored in the memory, at least part of the plurality of packet address tables also being duplicated in the cache; and

a cacheability register containing entries specifying cacheability of address ranges in the physical memory on a per packet address table ID basis.

13. The network element of claim 12, wherein the cacheability register entries are associated with memory allocations of physical memory, the cacheability register entries being created in response to memory allocation requests.

14. The network element of claim 12, further comprising a cache controller configured to use the entries in the cacheability register to implement a cacheability screening operation.

15. The network element of claim 14, wherein the cache controller is further configured to implement a cache replacement algorithm when a cache miss passes the cacheability screening operation.

16. The network element of claim 14, wherein the cacheability screening operation comprises comparing an address in physical memory with the entries in the cacheability register and determining, from one of the entries encompassing the address, whether the address is within a cacheable range of memory addresses.