METHOD AND APPARATUS FOR PAGE-LEVEL MONITORING

• US 20150095590A1
• Filed: 09/27/2013
• Published: 04/02/2015
• Est. Priority Date: 09/27/2013
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Jr., James D. Beany
• Inventors: Yamada, Koichi, Zhang, Bo, Lu, Jiwei Oliver, Beany, James D. Jr., Shanmugavelayutham, Palaniverlrajan
• Granted Patent: US 9,891,936 B2
• Time in Patent Office: Days
• US Class Current: 711/146
• CPC Class Codes: G06F 12/10 Address translation
• CPC Class Codes: G06F 12/1027 using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
• CPC Class Codes: G06F 2212/682 Multiprocessor TLB consistency
• CPC Class Codes: G06F 2212/683 Invalidation
• CPC Class Codes: G06F 9/4552 Involving translation to a different instruction set architecture, e.g. just-in-time translation in a JVM

Abstract

An apparatus and method for page level monitoring are described. For example, one embodiment of a method for monitoring memory pages comprises storing information related to each of a plurality of memory pages including an address identifying a location for a monitor variable for each of the plurality of memory pages in a data structure directly accessible only by a software layer operating at or above a first privilege level; detecting virtual-to-physical page mapping consistency changes or other page modifications to a particular memory page for which information is maintained in the data structure; responsively updating the monitor variable to reflect the consistency changes or page modifications; checking a first monitor variable associated with a first memory page prior to execution of first program code; and refraining from executing the first program code if the first monitor variable indicates consistency changes or page modifications to the first memory page.

Claims

1. A method for monitoring memory pages comprising:

storing information related to each of a plurality of memory pages including an address identifying a location for a monitor variable for each of the plurality of memory pages in a data structure directly accessible only by a software layer operating at or above a first privilege level;

detecting virtual-to-physical page mapping consistency changes or other page modifications to a particular memory page for which information is maintained in the data structure;

responsively updating the monitor variable to reflect the consistency changes or page modifications;

checking a first monitor variable associated with a first memory page prior to execution of first program code; and

refraining from executing the first program code if the first monitor variable indicates consistency changes or page modifications to the first memory page.

2. The method as in claim 1 wherein if the monitor variable does not indicate consistency changes or page modifications, then executing the first program code.

3. The method as in claim 1 wherein the first program code comprises translated binary code.

4. The method as in claim 1 wherein the data structure comprises a table with a separate row for each memory page.

5. The method as in claim 4 wherein monitor value comprises a Boolean data type with a FALSE value indicating consistency changes or page modifications.

6. The method as in claim 1 further comprising:

determining whether a virtual to physical mapping is present in a translation lookaside buffer and/or a page table for a current context; and

adding a new entry for a new memory page in the data structure only if a virtual to physical mapping is present in the translation lookaside buffer and/or the page table for the current context.

7. The method as in claim 1 further comprising:

re-validating entries for memory pages in the data structure within a new context'"'"'s address space responsive to an address space switch operation.

8. The method as in claim 1 further comprising:

invalidating one or more entries in the data structure in response to a flush of a corresponding entry in a translation lookaside buffer (TLB).

9. The method as in claim 8 wherein invalidating comprises identifying the one or more entries using a virtual address associated with the TLB flush operation.

10. A processor comprising:

first logic to store information related to each of a plurality of memory pages including an address identifying a location for a monitor variable for each of the plurality of memory pages in a data structure directly accessible only by a software layer operating at or above a first privilege level;

second logic to detect virtual-to-physical page mapping consistency changes or other page modifications to a particular memory page for which information is maintained in the data structure;

third logic to responsively update the monitor variable to reflect the consistency changes or page modifications;

fourth logic to check a first monitor variable associated with a first memory page prior to execution of first program code and refrain from executing the first program code if the first monitor variable indicates consistency changes or page modifications to the first memory page.

11. The processor as in claim 10 wherein if the monitor variable does not indicate consistency changes or page modifications, then executing the first program code.

12. The processor as in claim 10 wherein the first program code comprises translated binary code.

13. The processor as in claim 10 wherein the data structure comprises a table with a separate row for each memory page.

14. The processor as in claim 13 wherein monitor value comprises a Boolean data type with a FALSE value indicating consistency changes or page modifications.

15. The processor as in claim 10 further comprising:

fifth logic to add a new entry for a new memory page in the data structure only if a virtual to physical mapping is present in a translation lookaside buffer (TLB) and/or the page table for a current context.

16. The processor as in claim 10 further comprising:

fifth logic to re-validate entries for memory pages in the data structure within a new context'"'"'s address space responsive to an address space switch operation.

17. The processor as in claim 10 further comprising:

fifth logic to invalidate one or more entries in the data structure in response to a flush of a corresponding entry in a translation lookaside buffer (TLB).

18. The processor as in claim 17 wherein invalidating comprises identifying the one or more entries using a virtual address associated with the TLB flush operation.