ASSET MANAGEMENT DEVICE AND METHOD IN A HARDWARE PLATFORM

• US 20150095613A1
• Filed: 09/30/2014
• Published: 04/02/2015
• Est. Priority Date: 10/01/2013
• Status: Active Grant

• Current Assignee: Enyx SA
• Original Assignee: Enyx SA
• Inventors: KODDE, Edward
• Granted Patent: US 9,535,702 B2
• Time in Patent Office: Days
• US Class Current: 711/212
• CPC Class Codes: G06F 21/71 to assure secure computing or processing of information
• CPC Class Codes: G06F 21/79 in semiconductor storage media, e.g. directly-addressable memories
• CPC Class Codes: G06F 9/3824 Operand accessing
• CPC Class Codes: G06Q 40/04 Trading; Exchange, e.g. stocks, commodities, derivatives or currency exchange
• CPC Class Codes: H04L 9/0894 Escrow, recovery or storing of secret information, e.g. secret key escrow or cryptographic key storage

Abstract

An asset management method implemented on an integrated circuit uses a keys memory storing keys, each key being associated with an asset identifier, and a data memory storing asset information. The method comprises: receiving an input command for an asset comprising an asset identifier and asset information, computing addresses to Keys memory from the asset identifier, the computing addresses comprising calculating hashes from the asset identifier, finding or allocating an entry in keys memory for the asset, based on the computed set of addresses, depending on the input command, computing a data address to the data memory for the asset from the address and position in the keys memory at which an entry has been found or allocated for the asset; reading data in the data memory at the computed data address; and executing the input command based on the data read in the data memory at the data address.

Claims

1. An asset management method for managing assets, said method being implemented on an integrated circuit, wherein it uses a keys memory for storing keys, each key being associated with a respective asset identifier, and a data memory for storing asset information, said method comprising:

receiving an input command related to an asset comprising an asset identifier and a set of asset information associated with said asset,

computing a set of addresses to said Keys memory from said asset identifier, said step of computing a set of addresses comprising calculating hashes from said asset identifier,

finding or allocating an entry in said keys memory for said asset, based on said set of addresses, depending on the input command,

computing a data address to said data memory for said asset from the address and position in the keys memory at which an entry has been found or allocated for said asset,

reading data in the data memory at said computed data address, and

executing the input command based on the data word read in the data memory at said data address,

writing back the result to the keys and data memories.

2. The method of claim 1, using a plurality of memory chips used in parallel, and said step of computing an address comprises calculating a different hash for each memory.

3. The method of claim 1, wherein each key in said keys memory is associated with a presence bit, the method further comprising, in response to the allocation of an entry, setting the presence bit associated with the entry key to an active state.

4. The method of claim 3, wherein the couples formed by each key and the associated presence bit are arranged in the key memory, so that as many couples as possible are packed in each memory data word.

5. The method of claim 1, further comprising storing said asset information in association with said asset identifier in said data memory, in response to the allocation of said entry.

6. The method of claim 1, wherein said hashes are obtained by using the integrated circuit hardware multiplier to multiply the asset identifier by a given coefficient, which provides a data word, and selecting some of the bits of said data word.

7. The method of claim 1, wherein the integrated circuit further comprises at least one cache for keeping track of the last processed asset identifiers, as well as the addresses and positions at which the corresponding asset identifiers have been placed.

8. An asset management device implemented on an integrated circuit for managing assets, wherein said device comprises a keys memory for storing keys in association with respective asset identifiers and a data memory for storing asset information, the device further comprising:

an address generation core configured to, in response to the reception of an input command comprising an asset identifier and a set of asset information, compute a set of addresses to said keys memory from said asset identifier, said step of computing a set of addresses comprising calculating hashes from said asset identifier,

an entry allocation core for finding or allocating an entry in said keys memory for said asset, based on said set of addresses, depending on the input command,

a second address generation core configured to compute a data address to said data memory for said asset from the address and position at which an entry has been found or allocated in said keys memory, the data being read in the data memory at said data address,

an execution core for executing the input command based on the data read in the data memory at said data address and writing back the result.

9. The asset management device of claim 8, wherein said entry allocation core is configured to forward an auxiliary command to said second address generation core, said auxiliary command comprising the address and position at which an entry has been found or allocated for said asset, said second address generation core being configured to retrieve said address and position from said auxiliary command.

10. The asset management device of claim 8, wherein the first and second address generation cores, the entry allocation core, and the execution core are pipelined.

11. The asset management device of claim 8, wherein said keys memory is configured to store each key in association with a presence bit, the presence bit being set to an active state, in response to the allocation of the entry corresponding to the entry key associated with the presence bit.

12. The asset management device of claim 11, wherein the couples formed by each key memory and the associated presence bit are arranged in the key memory, so that as many couples as possible are packed in each memory data word.

13. The asset management device of claim 8, wherein the key memory and the data memory are provided on the same physical memory, said asset management device further comprising an arbiter entity so as to provide access to the physical memory from a first part responsible for keys management, including the first Address Generation Core and the entry allocation core, and a second part responsible for asset value management, including the second address generation core and the execution core, the arbiter entity being further configured to prevent both the key memory and the data memory from overlapping.

14. The asset management device of claim 8, wherein the hashes are obtained by using the integrated circuit hardware multiplier to multiply the asset identifier by a given coefficient, which provides a data word, and selecting some of the bits of said data word.