TECHNIQUES FOR PUTTING PLATFORM SUBSYSTEMS INTO A LOWER POWER STATE IN PARALLEL
First Claim
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1. An apparatus, comprising:
- processor circuitry; and
a power management component for execution on the processor circuitry to determine a sleep configuration state for each of a plurality of subsystems of a device having an associated subsystem sleep control register for entry into a lower power state, configure each of the associated subsystem sleep control registers with the sleep configuration state for each of the subsystems, and enable the sleep configuration state for each of the subsystems in parallel when transitioning to the lower power state.
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Abstract
Various embodiments are generally directed to an apparatus, method and other techniques for determining a sleep configuration state for each of a plurality of subsystems having an associated subsystem sleep control register for entry into a lower power state, configuring each of the associated subsystem sleep control registers with the sleep configuration state for each of the subsystems and enabling the sleep configuration state for each of the subsystems in parallel when transitioning to the lower power state.
17 Citations
23 Claims
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1. An apparatus, comprising:
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processor circuitry; and a power management component for execution on the processor circuitry to determine a sleep configuration state for each of a plurality of subsystems of a device having an associated subsystem sleep control register for entry into a lower power state, configure each of the associated subsystem sleep control registers with the sleep configuration state for each of the subsystems, and enable the sleep configuration state for each of the subsystems in parallel when transitioning to the lower power state. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. An article comprising a computer-readable storage medium containing a plurality of instructions that when executed enable a processor circuit to:
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determine a sleep configuration state for each of a plurality of subsystems having an associated subsystem sleep control register for entry into a lower power state; configure each of the associated subsystem sleep control registers with the sleep configuration state for each of the subsystems; and enable the sleep configuration state for each of the subsystems in parallel when transitioning to the lower power state. - View Dependent Claims (10, 11, 12, 13, 14, 15, 16)
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17. An apparatus, comprising:
logic to determine a sleep configuration state for each of a plurality of subsystems of a device having an associated subsystem sleep control register for entry into a lower power state, configure each of the associated subsystem sleep control registers with the sleep configuration state for each of the subsystems, and enable the sleep configuration state for each of the subsystems in parallel when transitioning to the lower power state. - View Dependent Claims (18, 19, 20, 21, 22, 23)
Specification