POWER CONTROL TECHNIQUES FOR INTEGRATED PCIE CONTROLLERS

• US 20150095687A1
• Filed: 09/27/2013
• Published: 04/02/2015
• Est. Priority Date: 09/27/2013
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Bryan L. Spry, Lily P. Looi, Shaun M. Conrad
• Inventors: SPRY, BRYAN L., CONRAD, Shaun M., LOOI, LILY P.
• Granted Patent: US 10,496,152 B2
• Time in Patent Office: Days
• US Class Current: 713/324
• CPC Class Codes: G06F 1/3253 Power saving in bus
• CPC Class Codes: G06F 1/3278 Power saving in modem or I/O interface
• CPC Class Codes: G06F 1/3287 by switching off individual functional units in the computer system
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management
• CPC Class Codes: Y02D 30/50 in wire-line communication networks, e.g. low power modes or reduced link rate

Abstract

Improved power control techniques for integrated peripheral component interconnect express (PCIe) controllers are described. In one embodiment, for example, a processor circuit may comprise an integrated PCIe controller and logic to detect a power reduction trigger, disable the integrated PCIe controller, and remove power from the integrated PCIe controller based on a power removal setting for the integrated PCIe controller. Other embodiments are described and claimed.

Claims

1. A processor circuit, comprising:

an integrated peripheral component interconnect express (PCIe) controller; and

logic, at least a portion of which is in hardware, the logic to detect a power reduction trigger, disable the integrated PCIe controller, and remove power from the integrated PCIe controller based on a power removal setting for the integrated PCIe controller.

2. The processor circuit of claim 1, the logic to store configuration information for the integrated PCIe controller.

3. The processor circuit of claim 1, the logic to remove power from the integrated PCIe controller by setting a power gate for the integrated PCIe controller to an open state.

4. The processor circuit of claim 1, the power reduction trigger indicating that a connection to an external power supply has been removed.

5. The processor circuit of claim 1, the logic to disable a PCIe graphics card communicating with the processor circuit over a PCIe link and activate integrated graphics circuitry of the processor circuit.

6. The processor circuit of claim 1, the power removal setting comprising a bit set by a basic input/output system (BIOS) during an initial boot sequence.

7. The processor circuit of claim 1, the logic to transition the processor circuit into a lower power state after removing power from the integrated PCIe controller.

8. The processor circuit of claim 1, comprising a PCIe input/output (I/O) module, the logic to disable the PCIe I/O module.

9. The processor circuit of claim 8, the logic to remove power from the PCIe I/O module when the power removal setting indicates that power may be removed from the PCIe I/O module, and place the PCIe I/O module into a low power state when the power removal setting indicates that power may not be removed from the PCIe I/O module.

10. An apparatus, comprising:

a processor circuit comprising an integrated peripheral component interconnect express (PCIe) controller to control a PCIe link;

an integrated device; and

logic, at least a portion of which is in hardware, the logic to detect a power reduction trigger, activate the integrated device, disable the integrated PCIe controller, and remove power from the integrated PCIe controller based on a power removal setting for the integrated PCIe controller.

11. The apparatus of claim 10, comprising a memory unit, the logic to store configuration information for the integrated PCIe controller in the memory unit.

12. The apparatus of claim 10, the logic to remove power from the integrated PCIe controller by setting a power gate for the integrated PCIe controller to an open state.

13. The apparatus of claim 10, the power reduction trigger indicating that a connection to an external power supply has been removed.

14. The apparatus of claim 10, the processor circuit to communicate with a PCIe device over the PCIe link, the logic to disable the PCIe device and activate the integrated device.

15. The apparatus of claim 10, the power removal setting comprising a bit set by a basic input/output system (BIOS) during an initial boot sequence.

16. The apparatus of claim 10, the logic to transition the processor circuit into a lower power state after removing power from the integrated PCIe controller.

17. The apparatus of claim 10, the processor circuit comprising a PCIe input/output (I/O) module, the logic to disable the PCIe I/O module.

18. The apparatus of claim 17, the logic to remove power from the PCIe I/O module when the power removal setting indicates that power may be removed from the PCIe I/O module, and place the PCIe I/O module into a low power state when the power removal setting indicates that power may not be removed from the PCIe I/O module.

19. The apparatus of claim 10, comprising a display and one or more RF transceivers.

20. At least one machine-readable medium comprising a set of instructions that, in response to being executed on a computing device, cause the computing device to:

detect a power reduction trigger;

disable an integrated peripheral component interconnect express (PCIe) controller of a processor circuit; and

remove power from the integrated PCIe controller based on a power removal setting for the integrated PCIe controller.

21. The at least one machine-readable medium of claim 20, comprising instructions that, in response to being executed on the computing device, cause the computing device to store configuration information for the integrated PCIe controller in a memory unit.

22. The at least one machine-readable medium of claim 20, comprising instructions that, in response to being executed on the computing device, cause the computing device to remove power from the integrated PCIe controller by setting a power gate for the integrated PCIe controller to an open state.

23. The at least one machine-readable medium of claim 20, the power reduction trigger indicating that a connection of the computing device to an external power supply has been removed.

24. The at least one machine-readable medium of claim 20, comprising instructions that, in response to being executed on the computing device, cause the computing device to disable a PCIe graphics card communicating with the processor circuit over a PCIe link and activate integrated graphics circuitry of the processor circuit.

25. The at least one machine-readable medium of claim 20, the power removal setting comprising a bit set by a basic input/output system (BIOS) during an initial boot sequence of the computing device.