SELF-ALIGNED TRENCH ISOLATION IN INTEGRATED CIRCUITS

• US 20150097245A1
• Filed: 10/08/2013
• Published: 04/09/2015
• Est. Priority Date: 10/08/2013
• Status: Active Grant

• Current Assignee: Infineon Technologies Batam PT (Infineon Technologies AG)
• Original Assignee: Spansion LLC (Infineon Technologies AG)
• Inventors: LU, Ching-Huang, Chan, Simon Siu-Sing, Sugino, Rinji, Xue, Lei, Ohtsuka, Kenichi
• Granted Patent: US 9,437,470 B2
• Time in Patent Office: Days
• US Class Current: 257/368
• CPC Class Codes: H01L 21/76224 using trench refilling with dielectric materials trench filling with polycristalline silicon H01L21/763; together with vertical isolation, e.g. trench refilling in a SOI substrate H01L21/76264
• CPC Class Codes: H01L 21/76237 introducing impurities in trench side or bottom walls, e.g. for forming channel stoppers or alter isolation behavior
• CPC Class Codes: H01L 21/8234 MIS technology , i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
• CPC Class Codes: H01L 21/823481 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 29/0638 for preventing surface leakage due to surface inversion layer, e.g. with channel stopper channel stoppers in combination with isolation region for integrated circuits H01L21/762
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/66484 with multiple gate, at least one gate being an insulated gate H01L29/66742 takes precedence
• CPC Class Codes: H01L 29/66537 using a self aligned punch through stopper or threshold implant under the gate region H01L29/66606 takes precedence
• CPC Class Codes: H01L 29/66825 with a floating gate H01L29/6684 takes precedence
• CPC Class Codes: H01L 29/66833 with a charge trapping gate insulator, e.g. MNOS transistors
• CPC Class Codes: H01L 29/7881 Programmable transistors with only two possible levels of programmation H01L29/7888 takes precedence
• CPC Class Codes: H01L 29/792 with charge trapping gate insulator, e.g. MNOS-memory transistors
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 43/30 characterised by the memory core region

Abstract

A system and method for providing electrical isolation between closely spaced devices in a high density integrated circuit (IC) are disclosed herein. An integrated circuit (IC) comprising a substrate, a first device, a second device, and a trench in the substrate and a method of fabricating the same are also discussed. The trench is self-aligned between the first and second devices and comprises a first filled portion and a second filled portion. The first fined portion of the trench comprises a dielectric material that forms a buried trench isolation for providing electrical isolation between the first and second devices. The self-aligned placement of the buried trench isolation allows for higher packing density without negatively affecting the operation of closely spaced devices in a high density IC.

Claims

1. An integrated circuit (IC), comprising:

a substrate;

a first device and a second device, the first and the second devices each comprising a gate structure; and

a trench in the substrate self-aligned between the gate structures of the first and second devices, the trench comprising;

a first filled portion comprising a dielectric material is configured to form a buried trench isolation between the first and second devices; and

a second filled portion comprising a conductive material.

2. The IC of claim 1, wherein each of the first and second devices further comprises a doped region that is substantially in contact with at least a part of the second filled portion.

3. The IC of claim 1, wherein each of the first and second devices further comprises a doped region that is substantially in contact with at least a part of the first and second filled portions.

4. The IC of claim 1, wherein a top surface of the first filled portion is substantially in contact with a bottom surface of the second filled portion.

5. The IC of claim 1, wherein the gate structure comprises:

a dielectric layer comprising a silicon oxide layer or a high-k dielectric layer, the dielectric layer being disposed on a top surface of the substrate; and

a gate layer comprising a polycrystalline silicon layer or a metal layer, the gate layer being disposed on the dielectric layer.

6. The IC of claim 1, wherein the gate structure comprises:

a dielectric layer comprising a silicon oxide layer, the dielectric layer being disposed on a top surface of the substrate; and

a first and second gate layer, the first and second gate layer each comprising a polycrystalline silicon layer or a metal layer.

7. The IC of claim 6, wherein:

the first gate layer is disposed on the dielectric layer; and

the second gate layer is disposed on the first gate layer.

8. The IC of claim 1, wherein the gate structure comprises:

a charge storing layer disposed between a first dielectric layer and a second dielectric layer, the first dielectric layer being disposed on a top surface of the substrate; and

a gate layer comprising a polycrystalline silicon layer or a metal layer, the gate layer being disposed on the second dielectric layer.

9. The IC of claim 8, wherein:

the charge storing layer comprises a nitride layer or a polycrystalline silicon layer; and

the first and second dielectric layers each comprises an oxide layer.

10. A method of fabricating an integrated circuit (IC), comprising:

defining an area on a substrate comprising patterning a first and second gate structure on a top surface of the substrate, the defined area being located between the first and second gate structure;

forming spacers on sidewalls of the first and second gate structures;

forming a self-aligned trench in the defined area, the self-aligned trench comprising a first and second portion, the second portion comprising an open end of the trench, the open end of the trench being on the top surface of the substrate;

filling the first portion with a dielectric material; and

filling the second portion with a conductive material.

11. The method of claim 10, wherein forming the self-aligned trench comprises etching the substrate in the defined area.

12. The method of claim 10, further comprising forming a first and second doped region, wherein:

the first doped region is in substantial contact with the first gate structure and with at least a part of the filled second portion; and

the second doped region is in substantial contact with the second gate structure and with at least another part of the filled second portion.

13. The method of claim 10, wherein filling the first portion comprises:

partially etching back spacers;

disposing a layer of dielectric material such that the layer of dielectric material at least fills the first and second portions; and

removing the layer of dielectric material from the second portion.

14. The method of claim 10, wherein filling the first portion comprises:

disposing a liner of a dielectric material along inner walls of the self-aligned trench;

disposing a layer of the dielectric material such that the layer of dielectric material at least fills the first and second portions; and

removing the liner and the layer of dielectric material from the second portion.

15. The method of claim 10, wherein filling the second portion comprises forming a layer of epitaxial material in the second portion, the epitaxial material comprising silicon or silicon germanium.

16. The method of claim 10, wherein filling the second portion comprises:

disposing a layer of conductive material such that the layer of conductive material at least fills the second portion, the conductive material comprising metal, silicide, silicon, amorphous silicon, or polycrystalline silicon; and

etching back the layer of conductive material.

17. The method of claim 10, wherein patterning the first and second gate structures comprises:

disposing a gate dielectric layer; and

disposing a gate layer on the gate dielectric layer, the gate layer comprising a polycrystalline silicon layer or a metal layer.

18. The method of claim 17, wherein disposing the gate dielectric layer comprises disposing an oxide layer or a high-k dielectric layer on the top surface of the substrate.

19. The method of claim 10, wherein patterning the first and second gate structures comprises:

disposing a first dielectric layer on the top surface of the substrate;

disposing a charge storing layer between the first dielectric layer and a second dielectric layer, the charge storing layer comprising a nitride layer or a polycrystalline silicon layer; and

disposing a gate layer on the second dielectric layer, the gate layer comprising a polycrystalline silicon layer or a metal layer.

20. A method of fabricating an integrated circuit (IC), comprising:

defining an area on a substrate comprising patterning a first and second partial gate structure on a top surface of the substrate, the defined area being located between the first and second partial gate structure;

forming a self-aligned trench in a substrate between the first and second partial gate structure, the trench comprising;

a first portion filled with a dielectric material, and

a second portion filled with a conductive material; and

forming a first and second complete gate structure.

21. The method of claim 20, wherein forming the first and second partial gate structure comprises:

disposing a gate dielectric layer; and

disposing a first gate layer on the gate dielectric layer, the gate layer comprising polycrystalline silicon.

22. The method of claim 20, wherein forming the self-aligned trench comprises:

etching the substrate between the formed first and second partial gate structure;

disposing a layer of dielectric material to fill the trench;

removing the layer of dielectric material from the second portion of the trench; and

disposing a layer of conductive material in the second portion of the trench.

23. The method of claim 20, wherein forming the first and second complete gate structure comprises disposing a second gate layer on the first gate layer, the second gate layer comprising a polycrystalline silicon layer or a metal layer.