METHOD OF MAKING A CMOS SEMICONDUCTOR DEVICE USING A STRESSED SILICON-ON-INSULATOR (SOI) WAFER

• US 20150099334A1
• Filed: 10/08/2013
• Published: 04/09/2015
• Est. Priority Date: 10/08/2013
• Status: Active Grant

• Current Assignee: STMicroelectronics International N.V. (STMicroelectronics NV)
• Original Assignee: STMicroelectronics Incorporated (STMicroelectronics NV)
• Inventors: LIU, QING, Loubet, Nicolas
• Granted Patent: US 9,018,057 B1
• Time in Patent Office: Days
• US Class Current: 438/199
• CPC Class Codes: H01L 21/02532 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/2251 Diffusion into or out of group IV semiconductors
• CPC Class Codes: H01L 21/7624 using semiconductor on insulator [SOI] technology H01L21/76297 takes precedence; manufacture of integrated circuits on insulating substrates H01L21/84; silicon on sapphire [SOS] technology H01L21/86
• CPC Class Codes: H01L 21/76264 SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
• CPC Class Codes: H01L 21/76283 Lateral isolation by refilling of trenches with dielectric material
• CPC Class Codes: H01L 21/8238 Complementary field-effect transistors, e.g. CMOS
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823814 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 21/823892 with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 21/845 including field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/1054 with a variation of the composition, e.g. channel with strained layer for increasing the mobility
• CPC Class Codes: H01L 29/161 including two or more of the elements provided for in group H01L29/16 , e.g. alloys H01L29/1604 takes precedence
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/4908 for thin film semiconductor, e.g. gate of TFT
• CPC Class Codes: H01L 29/66742 Thin film unipolar transistors
• CPC Class Codes: H01L 29/7842 means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate variation of the composition of the channel H01L29/1054
• CPC Class Codes: H01L 29/7848 : the means being located in the source/drain region, e.g. SiGe source and drain
• CPC Class Codes: H01L 29/7849 : the means being provided under the channel

Abstract

A method for forming a complementary metal oxide semiconductor (CMOS) semiconductor device includes providing a stressed silicon-on-insulator (sSOI) wafer comprising a stressed semiconductor layer having first and second laterally adjacent stressed semiconductor portions. The first stressed semiconductor portion defines a first active region. The second stressed semiconductor portion is replaced with an unstressed semiconductor portion. The unstressed semiconductor portion includes a first semiconductor material. The method further includes driving a second semiconductor material into the first semiconductor material of the unstressed semiconductor portion defining a second active region.

Claims

1. A method for forming a complementary metal oxide semiconductor (CMOS) semiconductor device comprising:

providing a stressed silicon-on-insulator (sSOI) wafer comprising a stressed semiconductor layer having first and second laterally adjacent stressed semiconductor portions, the first stressed semiconductor portion defining a first active region;

replacing the second stressed semiconductor portion with an unstressed semiconductor portion, the unstressed semiconductor portion comprising a first semiconductor material; and

driving a second semiconductor material into the first semiconductor material of the unstressed semiconductor portion defining a second active region.

2. The method according to claim 1 wherein the first semiconductor material comprises silicon, and the second semiconductor material comprises silicon and germanium.

3. The method according to claim 1 further comprising forming a mask layer over the first stressed semiconductor portion before replacing the second stressed semiconductor portion with the unstressed semiconductor portion.

4. The method according to claim 1 wherein replacing the second stressed semiconductor portion with the unstressed semiconductor portion comprises:

removing the second stressed semiconductor portion except for a second stressed semiconductor portion bottom layer; and

forming the unstressed semiconductor portion on the second stressed semiconductor portion bottom layer.

5. The method according to claim 4 further comprising annealing the second stressed semiconductor portion bottom layer before forming the unstressed semiconductor portion.

6. The method according to claim 4 further comprising annealing the unstressed semiconductor portion.

7. The method according to claim 1 wherein driving the second semiconductor material into the first semiconductor material comprises:

forming a second semiconductor layer comprising the second semiconductor material over the unstressed semiconductor portion; and

oxidizing the second semiconductor layer to drive the second semiconductor material into the first semiconductor material.

8. The method according to claim 1 further comprising:

forming first and second gate stacks over the first and second active regions, respectively;

forming first raised source and drain regions defining a first channel therebetween in the first active region under the first gate stack; and

forming second raised source and drain regions defining a second channel therebetween in the second active region under the second gate stack.

9. The method according to claim 8 wherein the first channel region is for an n-channel metal-oxide semiconductor field-effect transistor (nMOSFET) having a FinFET structure, and the second channel region is for a p-channel metal-oxide semiconductor field-effect transistor (pMOSFET) having a FinFET structure.

10. The method according to claim 1 wherein the stressed SOT wafer comprises a fully depleted SOT (FDSOI) wafer.

11. The method according to claim 1 wherein the first active region is for an n-channel metal-oxide semiconductor field-effect transistor, and the second active region is for a p-channel metal-oxide semiconductor field-effect transistor.

12. A method for forming a complementary metal oxide semiconductor (CMOS) semiconductor device comprising:

providing a stressed silicon-on-insulator (sSOI) wafer comprising a stressed semiconductor layer having first and second laterally adjacent stressed semiconductor portions, the first stressed semiconductor portion defining a first active region;

removing the second stressed semiconductor portion except for a second stressed semiconductor portion bottom layer;

forming the unstressed semiconductor portion on the second stressed semiconductor portion bottom layer, the unstressed semiconductor portion comprising a first semiconductor material; and

driving a second semiconductor material into the first semiconductor material of the unstressed semiconductor portion defining a second active region.

13. The method according to claim 12 wherein the first semiconductor material comprises silicon, and the second semiconductor material comprises silicon and germanium.

14. The method according to claim 12 further comprising forming a mask layer over the first stressed semiconductor portion before replacing the second stressed semiconductor portion with the unstressed semiconductor portion.

15. The method according to claim 12 further comprising annealing the second stressed semiconductor portion bottom layer before forming the unstressed semiconductor portion.

16. The method according to claim 12 further comprising annealing the unstressed semiconductor portion before driving the second semiconductor material into the first semiconductor material.

17. The method according to claim 12 wherein driving the second semiconductor material into the first semiconductor material comprises:

forming a second semiconductor layer comprising the second semiconductor material over the unstressed semiconductor portion; and

oxidizing the second semiconductor layer to drive the second semiconductor material into the first semiconductor material.

18. The method according to claim 12 further comprising:

forming first and second gate stacks over the first and second active regions, respectively;

forming first raised source and drain regions defining a first channel therebetween in the first active region under the first gate stack; and

forming second raised source and drain regions defining a second channel therebetween in the second active region under the second gate stack.

19. The method according to claim 18 wherein the first channel region is for an n-channel metal-oxide semiconductor field-effect transistor (nMOSFET) having a FinFET structure, and the second channel region is for a p-channel metal-oxide semiconductor field-effect transistor (pMOSFET) having a FinFET structure.

20. A method for forming a complementary metal oxide semiconductor (CMOS) semiconductor device comprising:

providing a stressed silicon-on-insulator (sSOI) wafer comprising a stressed semiconductor layer having first and second laterally adjacent stressed semiconductor portions, the first stressed semiconductor portion comprising silicon and defining a first active region;

replacing the second stressed semiconductor portion with an unstressed semiconductor portion, the unstressed semiconductor portion comprising silicon; and

driving silicon and germanium into the silicon of the unstressed semiconductor portion defining a second active region.

21. The method according to claim 20 further comprising forming a mask layer over the first stressed semiconductor portion before replacing the second stressed semiconductor portion with the unstressed semiconductor portion.

22. The method according to claim 20 wherein replacing the second stressed semiconductor portion with the unstressed semiconductor portion comprises:

removing the second stressed semiconductor portion except for a second stressed semiconductor portion bottom layer; and

forming the unstressed semiconductor portion on the second stressed semiconductor portion bottom layer.

23. The method according to claim 22 further comprising annealing the second stressed semiconductor portion bottom layer before forming the unstressed semiconductor portion.

24. The method according to claim 22 further comprising annealing the unstressed semiconductor portion.

25. The method according to claim 20 wherein driving the silicon and germanium into the silicon of the of the unstressed semiconductor portion comprises:

forming a second semiconductor layer comprising silicon and germanium over the unstressed semiconductor portion; and

oxidizing the second semiconductor layer to drive the silicon and germanium into the silicon.

26. The method according to claim 20 further comprising:

forming first and second gate stacks over the first and second active regions, respectively;

forming first raised source and drain regions defining a first channel therebetween in the first active region under the first gate stack; and

forming second raised source and drain regions defining a second channel therebetween in the second active region under the second gate stack.

27. The method according to claim 26 wherein the first channel region is for an n-channel metal-oxide semiconductor field-effect transistor (nMOSFET) having a FinFET structure, and the second channel region is for a p-channel metal-oxide semiconductor field-effect transistor (pMOSFET) having a FinFET structure.