SYSTEM AND METHOD FOR UNIFORM INTERLEAVING OF DATA ACROSS A MULTIPLE-CHANNEL MEMORY ARCHITECTURE WITH ASYMMETRIC STORAGE CAPACITY

• US 20150100746A1
• Filed: 10/03/2013
• Published: 04/09/2015
• Est. Priority Date: 10/03/2013
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: RYCHLIK, BOHUSLAV, WANG, FENG, ROHILLAH, ANWAR, BOOTH, SIMON
• Granted Patent: US 9,465,735 B2
• Time in Patent Office: Days
• US Class Current: 711/157
• CPC Class Codes: G06F 12/0607 Interleaved addressing

Abstract

Systems and methods for uniformly interleaving memory accesses across physical channels of a memory space with a non-uniform storage capacity across the physical channels are disclosed. An interleaver is arranged in communication with one or more processors and a system memory. The interleaver identifies locations in a memory space supported by the memory channels and is responsive to logic that defines virtual sectors having a desired storage capacity. The interleaver accesses the asymmetric storage capacity uniformly across the virtual sectors in response to requests to access the memory space.

Claims

1. A method for uniformly interleaving memory accesses to a memory space having anon-uniform storage capacity across physical channels, the method comprising:

identifying when a multiple-channel memory architecture is provided an asymmetric storage capacity across the physical channels;

using logic responsive to the identifying to define a number of virtual sectors of equal capacity; and

applying an interleaving function via an interleaver that accesses the asymmetric storage capacity uniformly across the virtual sectors in response to requests to access the memory space.

2. The method of claim 1, wherein a number of the physical channels is even and the number of virtual sectors of equal capacity is odd.

3. The method of claim 1, wherein a number of the physical channels is odd and the number of virtual sectors of equal capacity is even.

4. The method of claim 1, wherein the applying an interleaving function includes applying a spreading function.

5. The method of claim 4, wherein the spreading function dynamically distributes memory accesses in a defined ratio between physical channels over the memory space.

6. The method of claim 1, wherein the number of virtual sectors of equal capacity is programmable.

7. The method of claim 1, wherein the number of virtual sectors of equal capacity is fewer in number than a number of memory modules supporting the memory space.

8. The method of claim 1, wherein the number of virtual sectors of equal capacity is greater than a number of memory modules supporting the memory space.

9. The method of claim 1, wherein the memory space is supported by an odd number of memory modules of the same storage capacity.

10. The method of claim 1, wherein the memory space is supported by an even number of memory modules with at least one memory module having a storage capacity that is different from the storage capacity of the remaining memory modules.

11. The method of claim 1, wherein operations that access the memory space are supported at a data transfer rate to each of the physical channels that exceeds a non-interleaved data transfer rate.

12. The method of claim 1, wherein operations that access the memory space via a first physical channel are supported at a first data transfer rate and operations that access the memory space via a second physical channel are supported at a second data transfer rate that is different from the first data transfer rate.

13. The method of claim 12, wherein the first data transfer rate is a function of the second data transfer rate.

14. The method of claim 13, wherein the first data transfer rate and the second data transfer rate are determined based on a number of virtual sectors supported by a physical channel.

15. A computing device, comprising:

an interleaver arranged on a bus in communication with a processor and a system memory, the interleaver configured to identify locations in a memory space supported by at least two physical channels, the interleaver responsive to logic that identifies virtual sectors having a desired storage capacity; and

at least one memory module coupled to the at least two physical channels, respectively, the memory space having a non-uniform storage capacity between the physical channels, wherein the interleaver accesses the non-uniform storage capacity uniformly across the virtual sectors in response to requests to access the memory space.

16. The computing device of claim 15, further comprising:

a memory controller that signals the interleaver when the at least two physical channels are provided a disparate storage capacity between the at least two physical channels.

17. The computing device of claim 15, wherein the interleaver applies an N-way spreading function, where N is an integer, the N-way spreading function dynamically distributing memory accesses in a defined ratio between physical channels over the memory space.

18. The computing device of claim 15, wherein a number of virtual sectors of equal capacity is responsive to a parameter received in the processor.

19. The computing device of claim 15, wherein a number of virtual sectors of equal capacity is fewer in number than a number of memory modules supporting the memory space.

20. The computing device of claim 15, wherein the memory space is supported by an odd number of memory modules of the same storage capacity.

21. The computing device of claim 15, wherein operations that access the memory space are supported at a data transfer rate to each of the physical channels that exceeds a non-interleaved data transfer rate.

22. The computing device of claim 15, wherein operations that access the memory space via a first physical channel are supported at a first data transfer rate and operations that access the memory space via a second physical channel are supported at a second data transfer rate that is different from the first data transfer rate.

23. The computing device of claim 15, wherein a first data transfer rate is applied across a first set of physical channels and a second data transfer rate is applied across a second set of physical channels.

24. The computing device of claim 23, wherein the first data transfer rate and the second data transfer rate are determined as a function of a number of virtual sectors supported by a physical memory channel.

25. A computing device, comprising:

means for identifying a memory space arranged with non-uniform storage capacity across a multiple-channel memory access architecture;

means for identifying a number of virtual sectors of equal storage capacity in the memory space;

means for applying an interleaving function that uniformly accesses the virtual sectors in response to requests to access the memory space.

26. The computing device of claim 25, wherein the memory space is supported by an integer number of memory modules.

27. The computing device of claim 26, wherein at least one memory module has a storage capacity that is different than the storage capacity of the remaining memory modules.

28. The computing device of claim 25, wherein the means for applying an interleaving function applies an N-way spreading function, where N is an integer.

29. The computing device of claim 28, wherein the N-way spreading function dynamically distributes memory accesses in a defined ratio between physical channels over the memory space.

30. The computing device of claim 25, wherein a number of virtual sectors of equal capacity is responsive to a parameter received in a processor.

31. The computing device of claim 25, wherein a number of virtual sectors of equal capacity is fewer in number than a number of memory modules supporting the memory space.

32. The computing device of claim 25, wherein the memory space is supported by an odd number of memory modules of the same storage capacity.

33. The computing device of claim 25, wherein operations that access the memory space are supported at a data transfer rate to each of the physical channels that exceeds a non-interleaved data transfer rate.

34. The computing device of claim 25, wherein operations that access the memory space via a first physical channel are supported at a first data transfer rate and operations that access the memory space via a second physical channel are supported at a second data transfer rate that is different from the first data transfer rate.

35. The computing device of claim 34, wherein the first data transfer rate is a function of the second data transfer rate.

36. The computing device of claim 25, wherein a first data transfer rate is applied across a first set of physical channels and a second data transfer rate is applied across a second set of physical channels.

37. The computing device of claim 36, wherein the first data transfer rate and the second data transfer rate are determined as a function of a number of virtual sectors supported by a physical channel.

38. A non-transitory processor-readable medium having stored thereon processor instructions that when executed direct the processor to perform functions, comprising:

receiving an indication that a multiple-channel memory architecture is presently populated with memory modules that provide an asymmetric storage capacity across multiple channels;

in response to the indication, identifying a number of virtual sectors of equal capacity; and

applying an interleaving function that accesses the asymmetric storage capacity uniformly across the virtual sectors in response to requests to access the memory space.

39. The non-transitory processor-readable medium of claim 38, wherein at least one memory module has a storage capacity that is different than the storage capacity of the remaining memory modules.

40. The non-transitory processor-readable medium of claim 38, wherein the applying an interleaving function includes applying an N-way spreading function.

41. The non-transitory processor-readable medium of claim 40, wherein the N-way spreading function dynamically distributes memory accesses in a defined ratio between physical channels over the memory space.

42. The non-transitory processor-readable medium of claim 38, wherein the number of virtual sectors of equal capacity is programmable.

43. The non-transitory processor-readable medium of claim 42, wherein the number of virtual sectors of equal capacity is fewer in number than a number of memory modules supporting the memory space.

44. The non-transitory processor-readable medium of claim 38, wherein the memory space is supported by an odd number of memory modules of the same storage capacity.

45. The non-transitory processor-readable medium of claim 38, wherein operations that access the memory space are supported at a data transfer rate to each of the physical channels that exceeds a non-interleaved data transfer rate.

46. The non-transitory processor-readable medium of claim 38, wherein operations that access the memory space via a first physical channel are supported at a first data transfer rate and operations that access the memory space via a second physical channel are supported at a second data transfer rate that is different from the first data transfer rate.

47. The non-transitory processor-readable medium of claim 46, wherein the first data transfer rate is applied across a first set of physical channels and the second data transfer rate is applied across a second set of physical channels.