SHORT LOOP ATOMIC ACCESS

• US 20150100749A1
• Filed: 10/03/2013
• Published: 04/09/2015
• Est. Priority Date: 10/03/2013
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Jayakrishna P. S
• Inventors: Koker, Altug, S, JAYAKRISHNA P., K, Pattabhiraman
• Granted Patent: US 9,471,323 B2
• Time in Patent Office: Days
• US Class Current: 711/169
• CPC Class Codes: G06F 12/0831 using a bus scheme, e.g. with bus monitoring or watching means
• CPC Class Codes: G06F 9/3004 to perform operations on memory
• CPC Class Codes: G06F 9/3826 Bypassing or forwarding of data results, e.g. locally between pipeline stages or within a pipeline stage
• CPC Class Codes: G06F 9/3834 Maintaining memory consistency
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

Methods and systems may provide for receiving a request to perform an atomic operation and adding the atomic operation to an execution pipeline of an arithmetic logic unit (ALU) for one or more pending atomic operations if the one or more pending atomic operations are associated with a memory location identified in the request. Additionally, at least a portion of the execution pipeline may bypass the memory location. In one example, adding the atomic operation to the execution pipeline includes populating a linked list with a modification associated with the atomic operation, wherein the linked list is dedicated to the memory location.

Claims

1. A system comprising:

a display to visually present content;

a memory device including a memory location;

an arithmetic logic unit (ALU) including an atomic data buffer; and

a memory access controller coupled to the memory device and the ALU, the memory access controller including;

a request module to receive a request to perform an atomic operation with respect to the content, the request identifying the memory location, and

an atomic controller to add the atomic operation to an execution pipeline of the arithmetic logic unit (ALU) for one or more pending atomic operations in response to association of the one or more pending atomic operations with the memory location, wherein at least a portion of the execution pipeline bypasses the memory location and uses the atomic data buffer.

2. The system of claim 1, wherein the atomic controller includes a linked list module to populate a linked list with a modification associated with the atomic operation to add the atomic operation to the execution pipeline, wherein the linked list is to be dedicated to the memory location.

3. The system of claim 1, wherein the memory access controller further includes:

a memory interface to initiate a read from the memory location if no pending atomic operations are associated with the memory location and receive data from the memory location,

wherein the atomic module includes a pipeline module to create an execution pipeline for the memory location; and

a data module to send the data to the ALU and instruct the ALU to perform a modification associated with the atomic operation,

wherein the pipeline module is to instruct the ALU to store a result of the modification to the atomic data buffer of the ALU.

4. The system of claim 1, wherein the memory access controller further includes:

a result module to receive a result of the atomic operation from the ALU;

an operation response module to send the result to an originator of the request to perform the atomic operation,

wherein the atomic controller includes a pipeline module to identify a next atomic operation in the execution pipeline, instruct the ALU to perform a subsequent modification associated with the next atomic operation and send a pipeline command to the ALU; and

a memory interface to defer a write to the memory location until a result of a last atomic operation in the execution pipeline is received from the ALU.

5. The system of claim 4, wherein the pipeline command is to instruct the ALU to use data stored in the atomic data buffer to perform the subsequent modification.

6. The system of claim 1, wherein the memory access controller further includes:

a snoop monitor to detect a snoop to the memory location,

wherein the atomic controller is to halt formation of the execution pipeline in response to the snoop; and

a snoop response module to send a response to an originator of the snoop if all requests associated with the execution pipeline are complete,

wherein the atomic controller is to restart formation of the execution pipeline after the response is sent to the originator of the snoop.

7. A method of operating a memory access controller, comprising:

receiving a request to perform an atomic operation; and

adding the atomic operation to an execution pipeline of an arithmetic logic unit (ALU) for one or more pending atomic operations in response to association of the one or more pending atomic operations with a memory location identified in the request, wherein at least a portion of the execution pipeline bypasses the memory location.

8. The method of claim 7, wherein adding the atomic operation to the execution pipeline includes populating a linked list with a modification associated with the atomic operation, wherein the linked list is dedicated to the memory location.

9. The method of claim 7, further including:

initiating a read from the memory location if no pending atomic operations are associated with the memory location;

receiving data from the memory location;

creating an execution pipeline for the memory location;

sending the data to the ALU;

instructing the ALU to perform a modification associated with the atomic operation; and

instructing the ALU to store a result of the modification to an atomic data buffer of the ALU.

10. The method of claim 7, further including:

receiving a result of the atomic operation from the ALU;

sending the result to an originator of the request to perform the atomic operation;

identifying a next atomic operation in the execution pipeline;

instructing the ALU to perform a subsequent modification associated with the next atomic operation;

sending a pipeline command to the ALU; and

deferring a write to the memory location until a result of a last atomic operation in the execution pipeline is received from the ALU.

11. The method of claim 10, wherein the pipeline command instructs the ALU to use data stored in the atomic data buffer to perform the subsequent modification.

12. The method of claim 7, further including:

detecting a snoop to the memory location;

halting formation of the execution pipeline in response to the snoop;

sending a response to an originator of the snoop if all requests associated with the execution pipeline are complete; and

restarting formation of the execution pipeline after the response is sent to the originator of the snoop.

13. At least one computer readable storage medium comprising a set of instructions which, if executed by a memory access controller, cause the memory access controller to:

receive a request to perform an atomic operation; and

add the atomic operation to an execution pipeline of an arithmetic logic unit (ALU) for one or more pending atomic operations in response to association of the one or more pending atomic operations with a memory location identified in the request, wherein at least a portion of the execution pipeline bypasses the memory location.

14. The at least one computer readable storage medium of claim 13, wherein the instructions, if executed, cause the memory access controller to populate a linked list with a modification associated with atomic operation to add the atomic operation to the execution pipeline, wherein the linked list is to be dedicated to the memory location.

15. The at least one computer readable storage medium of claim 13, wherein the instructions, if executed, cause the memory access controller to:

initiate a read from the memory location if no pending atomic operations are associated with the memory location;

receive data from the memory location;

create an execution pipeline for the memory location;

send the data to the ALU;

instruct the ALU to perform a modification associated with the atomic operation; and

instruct the ALU to store a result of the modification to an atomic data buffer of the ALU.

16. The at least one computer readable storage medium of claim 13, wherein the instructions, if executed, cause the memory access controller to:

receive a result of the atomic operation from the ALU;

send the result to an originator of the request to perform the atomic operation;

identify a next atomic operation in the execution pipeline;

instruct the ALU to perform a subsequent modification associated with the next atomic operation;

send a pipeline command to the ALU; and

defer a write to the memory location until a result of a last atomic operation in the execution pipeline is received from the ALU.

17. The at least one computer readable storage medium of claim 16, wherein the pipeline command is to instruct the ALU to use data stored in the atomic data buffer to perform the subsequent modification.

18. The at least one computer readable storage medium of claim 13, wherein the instructions, if executed, cause a memory access controller to:

detect a snoop to the memory location;

halt formation of the execution pipeline in response to the snoop;

send a response to an originator of the snoop if all requests associated with the execution pipeline are complete; and

restart formation of the execution pipeline after the response is sent to the originator of the snoop.

19. A memory access controller, comprising:

a request module to receive a request to perform an atomic operation; and

an atomic controller to add the atomic operation to an execution pipeline of an arithmetic logic unit (ALU) for one or more pending atomic operations in response to association of the one or more pending atomic operations with a memory location identified in the request, wherein at least a portion of the execution pipeline bypasses the memory location.

20. The memory access controller of claim 19, wherein the atomic controller includes a linked list module to populate a linked list with a modification associated with the atomic operation to add the atomic operation to the execution pipeline, wherein the linked list is to be dedicated to the memory location.

21. The memory access controller of claim 19, further including:

a memory interface to initiate a read from the memory location if no pending atomic operations are associated with the memory location and receive data from the memory location,

wherein the atomic module includes a pipeline module to create an execution pipeline for the memory location; and

a data module to send the data to the ALU and instruct the ALU to perform a modification associated with the atomic operation,

wherein the pipeline module is to instruct the ALU to store a result of the modification to an atomic data buffer of the ALU.

22. The memory access controller of claim 19, further including:

a result module to receive a result of the atomic operation from the ALU;

an operation response module to send the result to an originator of the request to perform the atomic operation,

wherein the atomic controller includes a pipeline module to identify a next atomic operation in the execution pipeline, instruct the ALU to perform a subsequent modification associated with the next atomic operation and send a pipeline command to the ALU; and

a memory interface to defer a write to the memory location until a result of a last atomic operation in the execution pipeline is received from the ALU.

23. The memory access controller of claim 22, wherein the pipeline command is to instruct the ALU to use data stored in the atomic data buffer to perform the subsequent modification.

24. The memory access controller of claim 19, further including:

a snoop monitor to detect a snoop to the memory location,

wherein the atomic controller is to halt formation of the execution pipeline in response to the snoop; and

a snoop response module to send a response to an originator of the snoop if all requests associated with the execution pipeline are complete,

wherein the atomic controller is to restart formation of the execution pipeline after the response is sent to the originator of the snoop.