INCORPORATING A SPATIAL ARRAY INTO ONE OR MORE PROGRAMMABLE PROCESSOR CORES

• US 20150100757A1
• Filed: 04/14/2014
• Published: 04/09/2015
• Est. Priority Date: 05/31/2013
• Status: Active Grant

• Current Assignee: Microsoft Technology Licensing LLC (Microsoft Corporation)
• Original Assignee: Microsoft Corporation
• Inventors: Burger, Douglas C., Smith, Aaron, Duric, Milovan
• Granted Patent: US 9,792,252 B2
• Time in Patent Office: Days
• US Class Current: 712/20
• CPC Class Codes: G06F 15/7892 Reconfigurable logic embedded in CPU, e.g. reconfigurable unit
• CPC Class Codes: G06F 15/8023 Two dimensional arrays, e.g. mesh, torus
• CPC Class Codes: G06F 15/803 Three-dimensional arrays or hypercubes
• CPC Class Codes: G06F 9/30076 to perform miscellaneous control operations, e.g. NOP
• CPC Class Codes: G06F 9/3828 with global bypass, e.g. between pipelines, between clusters
• CPC Class Codes: G06F 9/3858 Result writeback, i.e. updating the architectural state or memory
• CPC Class Codes: G06F 9/3891 organised in groups of units sharing resources, e.g. clusters

Abstract

Functional units disposed in one or more processor cores are communicatively coupled using both a shared bypass network and a switched network. The shared bypass network enables the functional units to be operated conventionally for general processing while the switched network enables specialized processing in which the functional units are configured as a spatial array. In the spatial array configuration, operands produced by one functional unit can only be sent to a subset of functional units to which dependent instructions have been mapped a priori. The functional units may be dynamically reconfigured at runtime to toggle between operating in the general configuration and operating as the spatial array. Information to control the toggling between operating configurations may be provided in instructions received by the functional units.

Claims

1. A method of operating a processor comprising a plurality of functional units arranged in one or more cores, comprising:

configuring the functional units to operate in one of two discrete operational modes, a first discrete operational mode being implemented with the functional units in a standard core configuration using a first datapath, and a second discrete mode being implemented with the functional units in a spatial array configuration using a second datapath;

receiving a block of operating instructions, the operating instructions including an indication of the operational mode to be utilized for the block; and

dynamically reconfiguring the functional units at runtime to operate in one or the other discrete operational mode according to the received block of operating instructions.

2. The method of claim 1 in which the block of operating instructions further includes a static execution schedule for the spatial array configuration.

3. The method of claim 2 in which the static execution schedule is embedded in the received block.

4. The method of claim 3 in which the embedding includes replacing target bits in the operating instructions with static execution schedule information.

5. The method of claim 4 in which the static execution schedule information comprises routing paths or routing tables.

6. The method of claim 2 in which the static execution schedule is included in a separate received block.

7. The method of claim 2 in which the static execution schedule is partially implemented using embedded information in the received block and partially implemented using information in a separate received block.

8. The method of claim 1 further including implementing one or more data queues to store data for processing by the functional units, the data queue being accessible by the functional units when operating in either operational mode.

9. The method of claim 8 in which the data queue is a FIFO (first in, first out) queue.

10. The method of claim 1 in which the functional units are distributed across two distinct processing cores.

11. The method of claim 1 in which the functional units are distributed across four distinct processing cores.

12. The method of claim 1 which the functional units are distributed across one or more processing cores and in which the switched network further includes one or more repeaters respectively disposed between one or more of the cores.

13. The method of claim 1 further including coupling the functional units for inter-unit communication using two separate datapaths or two separate control paths.

14. A microarchitecture, comprising:

a plurality of arithmetic logic units (ALUs) distributed across one or more cores of a programmable processor;

a pipelined datapath providing inter-ALU connectivity while the processor is configured to perform standard processing;

a switched network providing inter-ALU connectivity configured to provide switchable configurations of ALUs, the ALUs switchably configurable for standard operations and for spatial array processing; and

an instruction set interface configured for receiving instructions, the instructions including operating instructions and control information for dynamically reconfiguring the ALUs during runtime.

15. The microarchitecture of claim 14 in which the switched network comprises a mesh.

16. The microarchitecture of claim 15 in which the mesh is one of 2D mesh or 3D mesh.

17. A method for operating one or more processor cores, comprising:

implementing a plurality of arithmetic logic units (ALUs) instantiated in the one or more processor cores;

implementing one or more fixed spatial arrays external to the one or more processor cores;

simultaneously interconnecting the ALUs using two sets of datapaths, a first set of datapaths being implemented at least in part using a bypass network, a second set of datapaths being implemented at least in part by a switched network; and

configuring the ALUs to operate (a) as a spatial array with inter-ALU communications being conducted over the switched network or (b) for general processing with inter-ALU communications being conducted over the bypass network.

18. The method of claim 17 further including dispatching special instruction blocks to the one or more external spatial arrays for processing.

19. The method of claim 17 further including receiving a block of operating instructions.

20. The method of claim 19 further including dynamically reconfiguring some of the ALUs at runtime according to the received block of operating instruction.