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METHOD AND APPARATUS FOR ENCODING AND DECODING A HIGH SPEED SHARED CONTROL CHANNEL

  • US 20150100863A1
  • Filed: 12/15/2014
  • Published: 04/09/2015
  • Est. Priority Date: 10/30/2006
  • Status: Abandoned Application
First Claim
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1. A Node-B comprising:

  • a processor configured to calculate cyclic redundancy check (CRC) bits for a data block;

    the processor configured to mask the CRC bits with wireless transmit/receive unit (WTRU) identity (ID) bits;

    the processor configured to attach the masked CRC bits to the data block; and

    a transmitter configured to transmit the data block.

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