Passivated and Faceted for Fin Field Effect Transistor

• US 20150102386A1
• Filed: 10/10/2013
• Published: 04/16/2015
• Est. Priority Date: 10/10/2013
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Chen, Yen-Yu, Shih, Chi-Yuan, Liu, Chi-Wen
• Granted Patent: US 9,287,262 B2
• Time in Patent Office: Days
• US Class Current: 257/192
• CPC Class Codes: H01L 21/823431 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823481 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 23/291 Oxides or nitrides or carbides, e.g. ceramics, glass
• CPC Class Codes: H01L 23/3171 the coating being directly applied to the semiconductor body, e.g. passivation layer H01L23/3178 takes precedence
• CPC Class Codes: H01L 27/0886 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/1054 with a variation of the composition, e.g. channel with strained layer for increasing the mobility
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/66818 the channel being thinned after patterning, e.g. sacrificial oxidation on fin
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7851 with the body tied to the substrate
• CPC Class Codes: H01L 29/7853 the body having a non-rectangular crossection
• CPC Class Codes: H01L 29/7854 with rounded corners
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A fin field effect transistor (FinFET), and a method of forming, is provided. The FinFET has a fin having one or more semiconductor layers epitaxially grown on a substrate. A first passivation layer is formed over the fins, and isolation regions are formed between the fins. An upper portion of the fins are reshaped and a second passivation layer is formed over the reshaped portion. Thereafter, a gate structure may be formed over the fins and source/drain regions may be formed.

Claims

1. A fin field effect transistor (FinFET) comprising:

a substrate;

a fin structure protruding from the substrate, the fin structure comprising one or more semiconductor layers, each of the semiconductor layers having a different lattice constant of a corresponding immediately underlying layer;

an isolation region adjacent opposing sidewalls of the fin structure, the fin structure having an upper portion extending above the isolation region, the upper portion having slanted sidewalls;

a first passivation layer interposed between the fin structure and the isolation region;

a second passivation layer on the upper portion of the fin structure; and

a gate structure overlying the upper portion of the fin structure.

2. The FinFET of claim 1, wherein the fin structure comprises a first silicon germanium layer over a substrate.

3. The FinFET of claim 2, wherein the fin structure comprises a germanium layer over the first silicon germanium layer.

4. The FinFET of claim 3, wherein the isolation region extends to an interface between the first silicon germanium layer and the germanium layer.

5. The FinFET of claim 2, wherein the fin structure comprises a second silicon germanium layer over the first silicon germanium layer, wherein a lattice constant of the first silicon germanium layer differs from a lattice constant of the second silicon germanium layer.

6. The FinFET of claim 5, wherein the isolation region extends to an interface between the first silicon germanium layer and the second silicon germanium layer.

7. The FinFET of claim 1, wherein the first passivation layer comprises an oxynitride.

8. The FinFET of claim 1, wherein the second passivation layer comprises an oxynitride.

9. The FinFET of claim 1, wherein the one or more semiconductor layers comprises a first semiconductor layer, and wherein the second passivation layer extends over sidewalls and an upper surface of the first semiconductor layer.

10. The FinFET of claim 9, wherein the first semiconductor layer is a silicon germanium layer and the second passivation layer is a silicon germanium oxynitride layer.

11. A method of forming a fin field effect transistor (FinFET), the method comprising;

providing a substrate;

forming one or more fins extending from the substrate, each of the one or more fins having one or more semiconductor layers overlying the substrate, each of the one or more fins having a lattice constant different than a lattice constant of an underlying layer;

forming a first passivation layer over the one or more fins;

forming isolation regions along opposing sidewalls of the one or more fins, the one or more fins extending above an uppermost surface of the isolation regions;

reshaping exposed portions of the one or more fins; and

forming a second passivation layer over the reshaped exposed portions of the one or more fins.

12. The method of claim 11, wherein the forming the one or more fins comprises:

forming one or more layers of semiconductor material on the substrate, each of the one or more layers of semiconductor material having a lattice constant different than adjoining layers; and

etching the one or more layers of semiconductor material, thereby forming the one or more fins.

13. The method of claim 12, wherein the etching comprises etching a portion of the substrate.

14. The method of claim 11, wherein the one or more semiconductor layers comprises a first semiconductor layer and a second semiconductor layer, the isolation regions extending to an interface between the first semiconductor layer and the second semiconductor layer.

15. The method of claim 11, wherein the one or more semiconductor layers comprises a single semiconductor layer, the second passivation layer extending over sidewalls and a top surface of the single semiconductor layer.

16. The method of claim 11, wherein the first passivation layer comprises an oxynitride.

17. The method of claim 11, wherein the second passivation layer comprises an oxynitride.

18. The method of claim 11, wherein the one or more semiconductor layers comprises a silicon germanium layer on the substrate and a germanium layer on the silicon germanium layer, and wherein the first passivation layer comprises silicon germanium oxynitride and the second passivation comprises germanium oxynitride.

19. The method of claim 11, wherein the one or more semiconductor layers comprises a Si_x1Ge_y1 layer on the substrate and a Si_x2Ge_y2 layer on the Si_x1Ge_y1, wherein x1 differs from x2 and y1 differs from y2.

20. The method of claim 11, wherein the one or more semiconductor layers comprises a silicon germanium layer on the substrate, the second passivation layer extending along sidewalls and an uppermost surface of the silicon germanium layer.