Semiconductor Device

• US 20150102404A1
• Filed: 10/15/2013
• Published: 04/16/2015
• Est. Priority Date: 10/15/2013
• Status: Active Grant

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Meiser, Andreas, Schloesser, Till, Hirler, Franz
• Granted Patent: US 9,401,399 B2
• Time in Patent Office: Days
• US Class Current: 257/334
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/0692 Surface layout
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/0865 Disposition
• CPC Class Codes: H01L 29/0882 Disposition
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7825 with trench gate electrode trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7835 with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
• CPC Class Codes: H01L 29/7838 without inversion channel, e.g. buried channel lateral MISFETs, normally-on lateral MISFETs, depletion-mode lateral MISFETs
• CPC Class Codes: H01L 29/8083 Vertical transistors SIT H01L29/7722

Abstract

A semiconductor device includes a transistor formed in a semiconductor substrate including a main surface. The transistor includes a source region, a drain region, a channel region, and a gate electrode. The source region and the drain region are disposed along a first direction, the first direction being parallel to the main surface. The channel region has a shape of a ridge extending along the first direction, the ridge including a top side and a first and a second sidewalls. The gate electrode is disposed at the first sidewall of the channel region, and the gate electrode is absent from the second sidewall of the channel region.

Claims

1. A semiconductor device comprising a transistor in a semiconductor substrate including a main surface, the transistor comprising:

a source region;

a drain region;

a channel region; and

a gate electrode, the source region and the drain region being disposed along a first direction, the first direction being parallel to the main surface, the channel region being disposed between the source region and the drain region, the channel region patterned into a ridge extending along the first direction by adjacent trenches extending in the first direction in the semiconductor substrate, the gate electrode being disposed in a first of one of the trenches adjacent to the channel region, and the gate electrode being absent from a second one of the trenches adjacent to the channel region.

2. The semiconductor device according to claim 1, wherein a conductive inversion layer is formed along the first sidewall in an on-state.

3. The semiconductor device according to claim 1, further comprising a channel separation element adjacent to a second sidewall of the channel region, the second sidewall being on a side of the second ones of the trenches.

4. The semiconductor device according to claim 3, wherein the channel separation element comprises a channel separation trench filled with a separation trench filling.

5. The semiconductor device according to claim 3, wherein the channel separation element comprises a channel separation trench including a conductive filling and a separation dielectric disposed between the conductive filling and the channel region.

6. The semiconductor device according to claim 5, wherein a thickness of the separation dielectric is larger than a thickness of a gate dielectric between the gate electrode and the channel region.

7. The semiconductor device according to claim 5, wherein the source region and the conductive filling of the channel separation trench are electrically connected to a source terminal.

8. The semiconductor device according to claim 1, further comprising a drift zone between the channel region and the drain region.

9. The semiconductor device according to claim 4, further comprising a drift zone and a field plate at the drift zone, wherein the field plate is connected to the channel separation trench.

10. The semiconductor device according to claim 1, wherein a width d of the ridge is:

d<

ld, wherein ld denotes a length of a depletion zone formed at an interface between the ridge and the gate electrode.

11. An integrated circuit comprising the semiconductor device according to claim 1.

12. A semiconductor device comprising a transistor formed in a semiconductor substrate comprising a main surface, the transistor comprising:

a source region;

a drain region;

a channel region;

a gate trench adjacent to a first sidewall of the channel region;

a gate conductive material disposed in the gate trench, the gate conductive material being connected to a gate terminal; and

a channel separation trench adjacent to a second sidewall of the channel region, the second sidewall facing the first sidewall via the channel region, the channel separation trench being filled with an insulating separation trench filling or having a conductive filling that is disconnected from the gate terminal,

wherein the source region and the drain region are disposed along a first direction, the first direction being parallel to the main surface.

13. The semiconductor device according to claim 12, wherein a conductive inversion layer is formed along the first sidewall in an on-state.

14. The semiconductor device according to claim 12, wherein the channel separation trench includes a conductive filling and a separation dielectric disposed between the conductive filling and the channel region.

15. The semiconductor device according to claim 14, wherein a thickness of the separation dielectric is larger than a thickness of a gate dielectric between the gate electrode and the channel region.

16. The semiconductor device according to claim 14, wherein the source region and the conductive filling of the channel separation trench are connected to a source terminal.

17. The semiconductor device according to claim 14, further comprising a field plate, wherein the field plate is connected to the conductive filling of the channel separation trench.

18. The semiconductor device according to claim 12, further comprising a drift zone between the channel region and the drain region.

19. An integrated circuit comprising the semiconductor device according to claim 12.

20. A semiconductor device comprising an array of transistors formed in a semiconductor substrate comprising a main surface, the array of transistors comprising:

a source region;

a drain region;

a plurality of channel regions;

a plurality of trenches adjacent to each of the channel regions, respectively, so that two trenches are adjacent to opposite sides of one of the channel regions, respectively, the plurality of trenches including gate trenches and channel separation trenches; and

a gate conductive material connected to a gate terminal, the gate conductive material being disposed in the gate trenches,

wherein the source region and the drain region are disposed along a first direction, the first direction being parallel to the main surface,

wherein at least one of the trenches is a channel separation trench, the channel separation trench being either filled with a dielectric material or having a conductive filling disconnected from the gate terminal.

21. The semiconductor device according to claim 20, wherein the gate trenches and the channel separation trenches are disposed in an alternating manner so that one gate trench and one channel separation trench is adjacent to different sidewalls of each of the channel regions.

22. The semiconductor device according to claim 21, wherein the channel separation trenches include first channel separation trenches filled with an insulating material and second channel separation trenches filled with a conductive filling and a separation dielectric layer between the conductive filling and the channel region.

23. An integrated circuit comprising the semiconductor device according to claim 20.